In recent years

as a IP integration method of complex System-on-chip

Network-on-chip (NoC) based on communication has gradually been known and accepted

so that became the hotspot of integrated circuit research. Not only the study of NoC technology

but also the researches on its test methods are crucial. This paper presents a parallel scheme of testing NoC router

which is designing a shared Build-In Self Test (BIST) controller to replace the special testing module

using improved multicast routing algorithm for transmitting test packets concurrently

adding the excitation circuit and the response analysis circuit to the circuit to be tested

and reusing NoC resources as test access mechanism to complete the parallel test for saving test cost. Though ecause test process and data transmission are executed in parallel

the scheme reduces the testing time. By improving testing algorithm

the fault coverage is improved

and fault location is realized. Experiments verified the validity of the test strategy.