The Design of Reconfigurable Cache Scheme in Multi-core Processor

XIE Jing; ZHANG Yu; WANG Qin; MAO Zhi-gang

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The Design of Reconfigurable Cache Scheme in Multi-core Processor

更新时间：2026-09-04

- The Design of Reconfigurable Cache Scheme in Multi-core Processor
- Vol. 33, Issue 12, Pages: 1-5(2016)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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谢憬, 章裕, 王琴, 毛志刚. 多核处理器片上可重构Cache系统及其机制设计[J]. 微电子学与计算机, 2016, 33(12): 1-5.

XIE Jing, ZHANG Yu, WANG Qin, et al. The Design of Reconfigurable Cache Scheme in Multi-core Processor[J]. 2016, 33(12): 1-5.
谢憬, 章裕, 王琴, 毛志刚. 多核处理器片上可重构Cache系统及其机制设计[J]. 微电子学与计算机, 2016, 33(12): 1-5. DOI：

XIE Jing, ZHANG Yu, WANG Qin, et al. The Design of Reconfigurable Cache Scheme in Multi-core Processor[J]. 2016, 33(12): 1-5. DOI：

摘要

针对多核处理器规模化数据访存与并行线程交叉数据使用的特性

提出了一种可重构Cache的设计方案

包含其基本硬件逻辑结构和工作机制; 同时提出了一种可在线动态重构Cache结构配置字生成的DCAC配置方法。实验证明

上述设计方案配合在线配置方法工作

能有效实现多核处理器系统根据不同的应用实时地配置共享Cache的组相联度

使得近处理器内核的Cache系统有效提升了命中率

在硬件开销增加4.07%的情况下

缺失代价平均下降约16.13%

从而达到了多核处理器性能优化的目标。

Abstract

To deal with massive and parallel data processing

the paper proposed a design solution of reconfigurable cache for multi-core processor.The work included the design of reconfigurable cache structure and its operation scheme

as well as a reconfiguration context word generation method

named as Dynamic Cache Associativity Configuration(DCAC)method.The experiments verified that with 4.07% overhead in hardware cost

the design solution won a 16.13% reduction of miss penalty in average for the core nearby caches with dynamic cache associativity reconfiguration method.

关键词

Keywords

references

Avakian A, Nafziger J, Panda A, et al. A reconfigurable architecture for multicore systems[C]//Parallel % amp; amp; Distributed Processing, Workshops and Phd Forum(IPDPSW), 2010IEEE International Symposium on. USA: Atlanta, IEEE, 2010: 1-8.

Zhang C, Vahid F, Najjar W. A highly configurable Cache architecture for embedded systems[C]//Computer Architecture, 2003. Proceedings. 30th Annual International Symposium on. USA, San Diegeo, IEEE, 2003: 136-146.

Manakkadu S, Dutta S. Bandwidth based performance optimization of Multi-threaded applications[C]//Parallel Architectures, Algorithms and Programming(PAAP), 2014 Sixth International Symposium on. China, Beijing, IEEE, 2014: 118-122.

Gordon-Ross A, Vahid F, Dutt N D. Fast configurable-Cache tuning with a unified second-level Cache[J]. Very Large Scale Integration(VLSI)Systems, IEEE Transactions on, 2009, 17(1): 80-91. DOI: 80

Modarressi M, Hessabi S, Goudarzi M. A reconfigurable Cache architecture for object-oriented embedded systems[C]//Electrical and Computer Engineering, CCECE'06. Canadian, IEEE, 2006: 959-962.

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Related Institution

College of Computer Science, Xi′an University of Posts and Telecommunications, Xi′an

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1 College of Computer Science, Zhejiang University of Technology

2 Zhijing College of Zhejiang University of Technology

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