An 11 bit 150 MS/s Sub-range SAR ADC IP for Wireless Transceiver

HE Xiu-ju; XUE Chun-ying; WANG Ya; LI Fu-le; ZHANG Chun; JIANG Xue-ping

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An 11 bit 150 MS/s Sub-range SAR ADC IP for Wireless Transceiver

更新时间：2026-09-04

- An 11 bit 150 MS/s Sub-range SAR ADC IP for Wireless Transceiver
- Vol. 34, Issue 5, Pages: 1-5(2017)
- 作者机构：
  
  1. 清华大学微电子所,北京,100084
  2. 全球能源互联网研究院,北京,102211
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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何秀菊, 薛春莹, 王亚, 李福乐, 张春, 姜学平. 一种用于无线收发机的11 bit 150 MS/sSub-range SAR ADC IP[J]. 微电子学与计算机, 2017, 34(5): 1-5, 11.

HE Xiu-ju, XUE Chun-ying, WANG Ya, et al. An 11 bit 150 MS/s Sub-range SAR ADC IP for Wireless Transceiver[J]. 2017, 34(5): 1-5.
何秀菊, 薛春莹, 王亚, 李福乐, 张春, 姜学平. 一种用于无线收发机的11 bit 150 MS/sSub-range SAR ADC IP[J]. 微电子学与计算机, 2017, 34(5): 1-5, 11. DOI：

HE Xiu-ju, XUE Chun-ying, WANG Ya, et al. An 11 bit 150 MS/s Sub-range SAR ADC IP for Wireless Transceiver[J]. 2017, 34(5): 1-5. DOI：

摘要

提出一个用于无线收发机的双通道11 bit 150 MS/s逐次逼近型(SAR)模数转换器(ADC).ADC的两通道都采用Sub-range SAR的结构

电路中使用自举开关采样

提高电路的线性度; 采用全动态比较器

以节省功耗; 使用基于等效门控环形振荡器的异步高速SAR逻辑

提高ADC的转换速度.此外

在CDAC中采用分裂电容设计以避免使用导通性不良的中间电压连接开关.本设计在Smic 55 nm Low-Leakage CMOS工艺下流片.IP总面积是0.3 mm

核的有效面积是0.046 mm.测试结果为: 在供电电压和参考电压为1.2 V

采样率为150 MS/s的情况下

单通道消耗2.04 mA的电流

SNDR为60.9 dB

FOM值为17.9 fJ/conv.-step.静态特性DNL和INL分别为+0.99/-0.81 LSB和+2.21/-1.37 LSB.

Abstract

An 11 bit 150 MS/s dual-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) IP for wireless transceiver is presented in this paper. Each channel adopts sub-range SAR architecture

which combines bootstrap switches for high linearity

gate-controlled ring oscillator (GCRO) for high speed and dynamic comparator for low power. In addition

division in Capacitive Digital-to-analog Converter (CDAC) avoids capacitors connecting to common-mode voltage (VCM) and the switch transistors incompletely switching on. The 11 bit 150 MS/s prototype is fabricated in smic 55 nm low leakage CMOS process. The active area of dual-channel ADC IP is 0.35 mm

while the core area is 0.046 mm. A single channel consumes 2.04 mA current and achieves an SNDR of 60.9 dB at 150 MS/s sample rate and 1.2V supply and reference

resulting in a FOM of 17.9 fJ/Conversion-step. Measured DNL and INL are +0.99/-0.81 LSB and +2.21/-1.37 LSB

respectively.

关键词

Keywords

references

Zhu Y, Chan C H, Sin S W, et al. A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation[C]//Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian. Jeju, South Korea, IEEE, 2011: 61-64.

Jeon Y D, Cho Y K, Nam J W, et al. A 9.15 mW 0.22 mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS[C]//Proceedings of the Custom Integrated Circuits Conference. USA, San Jose, California, 2010: 1-4.

Furuta M, Nozawa M, Itakura T. A 10 bit, 40 MS/s, 1.21 mW pipelined SAR ADC using single-ended 1.5-bit/cycle conversion technique[J]. Solid-State Circuits, 2011, 46(6): 1360-1370. DOI: 1360

Lien Y C. A 4.5 mW 8 b 750 MS/s 2 b/step asynchronous subranged SAR ADC in 28-nm CMOS technology[C]//VLSI Circuits (VLSIC), 2012 Symposium on. USA, Honolulu, Hawaii, IEEE, 2012: 88-89.

Lee B G, Tsang R M. A 10-bit 50 MS/s pipelined ADC with capacitor-sharing and variable-opamp[J]. Solid-State Circuits, 2009, 44(3): 883-890. DOI: 883

Lin Y Z, Liu C C, Huang G Y, et al. A 9 bit 150 MS/s 1.53 mW subranged SAR ADC in 90-nm CMOS[C]//VLSI Circuits (VLSIC), 2010 IEEE Symposium on. Greece, Lixouri, IEEE, 2010: 243-244.

Schinkel D, Mensink E, Klumperink E, et al. A double-tail latch-type voltage sense amplifier with 18ps setup+ hold time[C]//IEEE International Solid-state Circuits Conference. USA, San Francisco, 2007: 314-605.

Cao Z, Yan S, Li Y. A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 m CMOS[J]. Solid-State Circuits, 2009, 44(3): 862-873. DOI: 862

Meng Y, Lipeng W, Fule L, et al. An 8 bit 12 MS/s asynchronous successive approximation register ADC with an on-chip reference[J]. Journal of Semiconductors, 2013, 34(2): 025010. DOI: 025010

Danjo T, Yoshioka M, Isogai M, et al. A 6 bit, 1 GS/s, 9.9 mW, interpolated subranging ADC in 65-nm CMOS[J]. Solid-State Circuits, 2014, 49(3): 673-682. DOI: 673

Jin J, Gao Y, Sánchez-Sinencio E. An energy-efficient time-domain asynchronous 2 b/Step SAR ADC with a hybrid R-2R/C-3C DAC structure[J]. IEEE Journal of Solid-State Circuits, 2014, 49(6): 1383-1396. DOI: 1383

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