Five-Stage Pipeline Hardware Architecture Design for Deblocking Filter in HEVC

SHEN Gao-feng; CHEN Song; YANG Chen; YANG Can-mei

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Five-Stage Pipeline Hardware Architecture Design for Deblocking Filter in HEVC

更新时间：2026-09-04

- Five-Stage Pipeline Hardware Architecture Design for Deblocking Filter in HEVC
- Vol. 33, Issue 10, Pages: 1-6(2016)
- 作者机构：
  
  1. 中国科学技术大学电子科学与技术系,安徽,合肥,230027
  2. 中国科学技术大学先进技术研究院,安徽,合肥,230027
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
- 稿件说明：
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沈高峰, 陈松, 杨晨, 杨灿美. 基于五级流水线的HEVC DBF模块硬件架构设计[J]. 微电子学与计算机, 2016, 33(10): 1-6.

SHEN Gao-feng, CHEN Song, YANG Chen, et al. Five-Stage Pipeline Hardware Architecture Design for Deblocking Filter in HEVC[J]. 2016, 33(10): 1-6.
沈高峰, 陈松, 杨晨, 杨灿美. 基于五级流水线的HEVC DBF模块硬件架构设计[J]. 微电子学与计算机, 2016, 33(10): 1-6. DOI：

SHEN Gao-feng, CHEN Song, YANG Chen, et al. Five-Stage Pipeline Hardware Architecture Design for Deblocking Filter in HEVC[J]. 2016, 33(10): 1-6. DOI：

摘要

DBF (Deblocking Filter) 是HEVC解码器中复杂度较高的一个部分

它的处理速度直接影响到整个视频解码器的性能.提出了一种基于五级流水线操作的高性能DBF模块硬件架构

为了消除流水线操作中数据依赖的影响

选取了16×8像素单元作为基本处理单元

占用很少的内部存储器资源.硬件架构使用Verilog硬件描述语言实现

并通过Xilinx-ISE工具进行了电路综合.结果表明

此电路架构能够在48.1 MHz的工作频率下

达到4 096×2 048分辨率60 fps高清视频的实时解码要求.

Abstract

Deblocking Filter (DBF) is one of the components which have high computational complexity in HEVC decoder. Its processing speed directly affects the whole performance of video decoders. This paper proposes a high performance five-stage-pipeline-based hardware Architecture of DBF. In order to eliminate the influence of data dependency in the pipeline operation

a 16×8 pixels unit is chosen as basic processing unit. This unit occupies very little internal storage resources. The proposed hardware Architecture is implemented in Verilog-HDL. The implementation is synthesized by Xilinx ISE tool. The results show that the proposed architecture can meet requirement of real-time decoding 4 096×2 048@60fps high definition video under an operating frequency of 48.1 MHz.

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references

Jiayi Z H U, Dajiang Z. A high performance HEVC de-blocking filter and SAO architecture for UHDTV decoder[J]. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2013, 96(12): 2612-2622. DOI: 2612

Srinivasarao B K N, Chakrabarti I, Ahmad M N. High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter[J]. Circuits, Devices % Systems, IET, 2015, 9(5): 377-383. DOI: 377

Cheng W, Fan Y, Lu Y H, et al. A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application[C]//Circuits and Systems (ISCAS), 2015 IEEE International Symposium on. Portugal. Lisbon, IEEE, 2015: 605-608.

Norkin A, Bjontegaard G, Fuldseth A, et al. HEVC deblocking filter[J]. Circuits and Systems for Video Technology, IEEE Transactions on, 2012, 22(12): 1746-1754. DOI: 1746

Sullivan G J, Ohm J R, Han W J, et al. Overview of the high efficiency video coding (HEVC) standard[J]. Circuits and Systems for Video Technology, IEEE Transactions on, 2012, 22(12): 1649-1668. DOI: 1649

Ozcan E, Adibelli Y, Hamzaoglu I. A high performance deblocking filter hardware for high efficiency video coding[J]. Consumer Electronics, IEEE Transactions on, 2013, 59(3): 714-720. DOI: 714

Vanne J, Viitanen M, Hamalainen T D, et al. Comparative rate-distortion-complexity analysis of HEVC and AVC video codecs[J]. Circuits and Systems for Video Technology, IEEE Transactions on, 2012, 22(12): 1885-1898. DOI: 1885

Diniz C M, Shafique M, Dalcin F V, et al. A deblocking filter hardware architecture for the high efficiency video coding standard[C]//Proceedings of the 2015 Design, Automation % Test in Europe Conference % Exhibition. California, EDA Consortium, 2015: 1509-1514.

ITU. ITU-T Recommendation H. 265. High efficiency video coding[S]. Geneva, Switzerland: Telecommunication Standardization Sector, 2013.

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