A Design Pattern Targeting to Simplifying Pipeline Design Used on Course-Grained Reconfigurable Processor

ZHOU Jun-yu; ZHAO Zhong-yuan; SHENG Wei-guang; HE Wei-feng

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A Design Pattern Targeting to Simplifying Pipeline Design Used on Course-Grained Reconfigurable Processor

更新时间：2026-09-04

- A Design Pattern Targeting to Simplifying Pipeline Design Used on Course-Grained Reconfigurable Processor
- Vol. 33, Issue 9, Pages: 6-9(2016)
- 作者机构：
  
  上海交通大学微电子学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
- 稿件说明：
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周君宇, 赵仲元, 绳伟光, 何卫锋. 一种针对可重构处理器流水线简化编程的设计范式[J]. 微电子学与计算机, 2016, 33(9): 6-9.

ZHOU Jun-yu, ZHAO Zhong-yuan, SHENG Wei-guang, et al. A Design Pattern Targeting to Simplifying Pipeline Design Used on Course-Grained Reconfigurable Processor[J]. 2016, 33(9): 6-9.
周君宇, 赵仲元, 绳伟光, 何卫锋. 一种针对可重构处理器流水线简化编程的设计范式[J]. 微电子学与计算机, 2016, 33(9): 6-9. DOI：

ZHOU Jun-yu, ZHAO Zhong-yuan, SHENG Wei-guang, et al. A Design Pattern Targeting to Simplifying Pipeline Design Used on Course-Grained Reconfigurable Processor[J]. 2016, 33(9): 6-9. DOI：

摘要

提出了一种面向可重构处理器流水线的设计范式

并在clang编译架构的基础上添加新的语法

使得用新语法编写流水线程序的时候

能把代码量压缩为原来的10%~20%

并且让代码结构更加清晰和便于理解.

Abstract

This paper propose a new design pattern for simplifying the pipeline design used on Course-Grained Reconfigurable Processor and develop a new compiler based on the clang system. Experiment results show that the amount of code decrease to 10%~20% after applying this designed pattern. Futher more

the new design pattern makes the code clearer and more comprehensive.

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Keywords

references

Mirsky E, DeHon A. MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources[C]//FPGAs for Custom Computing Machines, 1996. IEEE Symposium on. Napa Vally, IEEE, 1996: 157-166.

International organization for standardization, ISO/IEC 9899: 1999, Programming Languages-C[S]. Geneva, Switzerland, ISO, 1999.

Lattner C. LLVM and Clang: Next generation compiler technology[C]//The BSD Conference. Canada, Outawa, 2008: 1-2.

Dieffenderfer J N, Kalla R N. Ping-pong data buffer for transferring data from one data bus to another data bus: US. Patent 5, 224, 213[P]. 1993-06-29.

Gordon M L, Thies W, Amarasinghe S. Exploiting coarse-grained task, data, and pipeline parallelism in stream programs[J]. ACM SIGOPS Operating Systems Review, 2006, 40(5): 151-162. DOI: 151

楼杰超, 绳伟光, 何卫锋, 等. 异构粗粒度可重构处理器的自动任务编译器框架设计[J]. 微电子学与计算机, 2015, 32(8): 23-25. DOI: 23

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