Bad-Die Recycling Technique for Yield Enhancement of Three-Dimensional Memories

LIU Jun; WANG Tang-ya; REN Fu-ji

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Bad-Die Recycling Technique for Yield Enhancement of Three-Dimensional Memories

更新时间：2026-09-04

- Bad-Die Recycling Technique for Yield Enhancement of Three-Dimensional Memories
- Vol. 33, Issue 10, Pages: 7-12(2016)
- 作者机构：
  
  1. 合肥工业大学计算机与信息学院,安徽,合肥,230009
  2. 情感计算与先进智能机器安徽省重点实验室机构,安徽,合肥,230009
  3. 日本德岛大学先端技术科学教育部, 日本德岛 7708502
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
- 稿件说明：
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刘军, 王堂亚, 任福继. 故障芯片重利用的三维存储器成品率提高方法[J]. 微电子学与计算机, 2016, 33(10): 7-12, 18.

LIU Jun, WANG Tang-ya, REN Fu-ji. Bad-Die Recycling Technique for Yield Enhancement of Three-Dimensional Memories[J]. 2016, 33(10): 7-12.
刘军, 王堂亚, 任福继. 故障芯片重利用的三维存储器成品率提高方法[J]. 微电子学与计算机, 2016, 33(10): 7-12, 18. DOI：

LIU Jun, WANG Tang-ya, REN Fu-ji. Bad-Die Recycling Technique for Yield Enhancement of Three-Dimensional Memories[J]. 2016, 33(10): 7-12. DOI：

摘要

提出了一种对故障芯片进行重新利用以提高三维存储器成品率的方法.该方法首先将存储块划分为多个存储子块

然后对存储芯片进行绑定前的测试以获取存储芯片的故障分布信息

从而获取存储芯片中有故障的存储子块数量

并根据所提的芯片选择算法来选定合适的存储芯片进行绑定.接着在三维存储器中选择一个无故障的存储块作为全局冗余

利用全局冗余中的存储子块对三维存储器中有故障的存储子块进行修复.实验结果表明

所提方法有效的提高了三维存储器的成品率.

Abstract

In order to make the best of the discarded bad dies

a yield enhancement technique by bad-die recycling for three-dimensional memory is proposed. In the presented technique

each block is divided into several sub-blocks firstly. After that

every die must go through the process of pre-bond test to get the fault information of blocks in a die

and then counting the number of the faulty sub-blocks in a die. Finally a fault-free block is chosen as global redundancy

and the sub-blocks in the global redundancy are used to repair faulty sub-blocks. The experimental results show that the proposed methodology is effective for yield enhancement of the three-dimensional memory.

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references

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Huang R F, Li J F, Yeh J C, et al. A simulator for evaluating redundancy analysis algorithms of repairable embedded memories[C]//Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on. France, Bendor, IEEE, 2002: 68-75.

Jiang L, Ye R, Xu Q. Yield enhancement for 3D-stacked memory by redundancy sharing across dies[C]//Proceedings of the International Conference on Computer-Aided Design. China, Yiwu, IEEE Press, 2010: 230-234.

Lee J, Park K, Kang S. A Die-selection method using search-space conditions for yield enhancement in 3D memory[J]. ETRI Journal, 2011, 33(6): 904-913. DOI: 904

Kang W, Lee C, Cho K, et al. A die selection and matching method with two stages for yield eehancement of 3-D memories[C]//Test Symposium (ATS), 2013 22nd Asian. Taiwan, Yilan, IEEE, 2013: 301-306.

Chou Y F, Kwai D M, Shieh M D, et al. Reactivation of spares for off-chip memory repair after die stacking in a 3-D IC with TSVs[J]. Circuits and Systems Ⅰ: Regular Papers, IEEE Transactions on, 2013, 60(9): 2343-2351. DOI: 2343

Chou Y F, Kwai D M, Wu C W. Yield enhancement by bad-die recycling and stacking with though-silicon vias[J]. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2011, 19(8): 1346-1356. DOI: 1346

Rab M T, Bawa A, Touba N. Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assembly[C]//Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012 IEEE International Symposium on. USA, Austin, IEEE, 2012: 178-181.

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