A High-Precision SRAM Timing Parameter Measurement Circuit Based on Delay Line

JIANG Bin; ZHANG Min-min; WANG Qin; JIANG Jian-fei; MAO Zhi-gang

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A High-Precision SRAM Timing Parameter Measurement Circuit Based on Delay Line

更新时间：2026-09-04

- A High-Precision SRAM Timing Parameter Measurement Circuit Based on Delay Line
- Vol. 34, Issue 6, Pages: 18-20(2017)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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姜彬, 张敏敏, 王琴, 蒋剑飞, 毛志刚. 基于延时链的高精度SRAM时序参数测量电路[J]. 微电子学与计算机, 2017, 34(6): 18-20, 25.

JIANG Bin, ZHANG Min-min, WANG Qin, et al. A High-Precision SRAM Timing Parameter Measurement Circuit Based on Delay Line[J]. 2017, 34(6): 18-20.
姜彬, 张敏敏, 王琴, 蒋剑飞, 毛志刚. 基于延时链的高精度SRAM时序参数测量电路[J]. 微电子学与计算机, 2017, 34(6): 18-20, 25. DOI：

JIANG Bin, ZHANG Min-min, WANG Qin, et al. A High-Precision SRAM Timing Parameter Measurement Circuit Based on Delay Line[J]. 2017, 34(6): 18-20. DOI：

摘要

本文提出并实现了一种用于测量SRAM时序参数的延时链电路

在SMIC 130 nm工艺下精度可以达到4.9 ps.该延时链电路包括可调链路和固定链路

可调链路由可编程粗调单元和精调单元组成

固定链路由固定单元组成.并将待测SRAM和测量电路集成入SOC系统中

从而实现SRAM的建立、保持和读写时间切换测量的功能.

Abstract

The paper mainly introduced a delay line circuit for SRAM timing parameter measurement. Under the process of SMIC 130nm

the precision could reach 4.9 ps. The delay chain circuit includes programmable and fixed path. Programmable path includes programmable coarse block and fine block; fixed path is made of fixed units. SRAM to be measured and measurement circuit are integrated to a SOC system so as to realize the SRAM function of establishment

hold and access time measurement.

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references

Murakami D, Kuwabara T. A digitally programmable delay line and duty cycle controller with picosecond resolution[C] // Bipolar Circuits and Technology Meeting, Proceedings of the 1991. Minneapolis, USA, IEEE, 1991: 218-221.

Lee M K, Teng W K, Krishnasamy R K, et al. Delay-line based embedded memory access time measurement: Circuit, implementation and characterization techniques[C]// Quality Electronic Design (ASQED), 2012 4th Asia Symposium on. Penang, Malaysia, IEEE, 2012: 259-264.

Yuan X, Owczarczyk P, Drake A J, et al. Design considerations for reconfigurable delay circuit to emulate system critical paths[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(11): 2714-2718. DOI: 2714

Pei S, Li H, Li X. A low overhead on-chip path delay measurement circuit[C]//2009 Asian Test Symposium. IEEE, 2009: 145-150.

Tsai M C, Cheng C H, Yang C M. An all-digital high-precision built-in delay time measurement circuit[C] // 26th IEEE VLSI Test Symposium (vts 2008). San Diego, California, IEEE, 2008: 249-254.

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Related Institution

University of Chinese Academy of Sciences

Technology and Engineering Center for Space Utilization, Chinese Academy of Sciences

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1 Department of Microelectronics, Tsinghua University

2 College of Science, Beijing Information Science&Technology University

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