A SRAM Bitcell Design for Ultra-Low Supply Application

LIU Bing-yan; CAI Jiang-zheng; HEI Yong

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A SRAM Bitcell Design for Ultra-Low Supply Application

更新时间：2026-09-04

- A SRAM Bitcell Design for Ultra-Low Supply Application
- Vol. 33, Issue 9, Pages: 15-18(2016)
- 作者机构：
  
  中国科学院机构微电子研究所,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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刘冰燕, 蔡江铮, 黑勇. 应用于超低电压下的SRAM存储单元设计[J]. 微电子学与计算机, 2016, 33(9): 15-18, 23.

LIU Bing-yan, CAI Jiang-zheng, HEI Yong. A SRAM Bitcell Design for Ultra-Low Supply Application[J]. 2016, 33(9): 15-18.
刘冰燕, 蔡江铮, 黑勇. 应用于超低电压下的SRAM存储单元设计[J]. 微电子学与计算机, 2016, 33(9): 15-18, 23. DOI：

LIU Bing-yan, CAI Jiang-zheng, HEI Yong. A SRAM Bitcell Design for Ultra-Low Supply Application[J]. 2016, 33(9): 15-18. DOI：

摘要

提出一种能够工作在低电压下的SRAM存储单元

单元采用8T结构

在传统6T结构的基础上增加两个串联的NMOS构成读出端口

传统6T结构中背靠背反相器采用高阈值晶体管.采用Smic130 nm工艺仿真结果显示

提出的8T结构能够在最低0.3 V下正常操作

单元的读写噪声容限

保持噪声容限

相比传统6管结构显著提升

并且低电压下静态功耗方面均比传统6管结构降低60%~70%.

Abstract

This paper presents a novel SRAM bitcell structure which is applied for ultra-low voltage. The bitcell is composed of 8 transistors

two additional NMOS transistors in series is added to traditional 6T structure as a read out port. Besides

the back to back to inverter is designed by high threshold voltage transistors. Simulations in simic 130 nm process are operated. The simulation results show that the hold and read static noise margin of proposed bitcell have enhanced greatly comparing to conventional 6T

additionally

this new bitcell can operate correctly in ultra-low voltage region. Comparing to conventional 6T cell

the static power consuming of this bitcell is reduced by 60%~70% in low voltage region.

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Keywords

references

Chang M H, Chiu Y T, Lai S L, et al. A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS[C]//Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design. Italy, Rome, IEEE Press, 2011: 291-296.

Yabuuchi M. A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist[C]// VLSI Circuits, 2009 Symposium on. Japan, Kyoto, 2009: 158-159.

Tawfik S A, Kursun V. Low power and robust 7T dual-Vt SRAM circuit[C]//Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on. Seattle. Washington, USA, IEEE, 2008: 1452-1455.

Sharma V, Cosemans S, Ashouei M, et al. A 4.4 pJ/access 80 MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier redundancy[J]. Solid-State Circuits, 2011, 46(10): 2416-2430. DOI: 2416

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Wu J J, Chen Y H, Chang M F, et al. A large sigma VTH/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme[J]. Solid-State Circuits, IEEE Journal of, 2011, 46(4): 815-827. DOI: 815

Liu Z, Kursun V. Characterization of a novel nine-transistor SRAM cell[J]. IEEE Transactions on Very Large Scale Integration Systems, 2008, 16(4): 488-492. DOI: 488

Sinangil Y, Chandrakasan A P. A 128 kbit SRAM with an embedded energy monitoring circuit and sense-amplifier offset compensation using body biasing[J]. IEEE Journal of Solid-State Circuits, 2014, 49(11): 2730-2739. DOI: 2730

Wang Jiajing, Nalam S, Calhoun B H. Analyzing static and dynamic write margin for nanometer SRAMs[M]. UK, Cardiff, Low Power Electronics and Design, International Symposium on ACM Press, 2008: 129-134.

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