The High-Throughput ASIC Implementation of SHA-1 Algorithm

DU Xiao-jing; LI Shu-guo

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The High-Throughput ASIC Implementation of SHA-1 Algorithm

更新时间：2026-09-04

- The High-Throughput ASIC Implementation of SHA-1 Algorithm
- Vol. 33, Issue 10, Pages: 19-23(2016)
- 作者机构：
  
  1. 清华大学微电子学研究所,北京,100084
  2. 清华信息科学与技术国家实验室,北京,100084
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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杜晓婧, 李树国. SHA-1算法的高速ASIC实现[J]. 微电子学与计算机, 2016, 33(10): 19-23, 27.

DU Xiao-jing, LI Shu-guo. The High-Throughput ASIC Implementation of SHA-1 Algorithm[J]. 2016, 33(10): 19-23.
杜晓婧, 李树国. SHA-1算法的高速ASIC实现[J]. 微电子学与计算机, 2016, 33(10): 19-23, 27. DOI：

DU Xiao-jing, LI Shu-guo. The High-Throughput ASIC Implementation of SHA-1 Algorithm[J]. 2016, 33(10): 19-23. DOI：

摘要

SHA-1算法是一种国际标准的安全杂凑算法.为提高SHA-1算法的吞吐率

提出了一种新的五合一架构

该架构使SHA-1算法的迭代压缩由原来的80轮变为16轮

并可使每轮中某些f函数和部分加法移到关键路径外

从而缩短了关键路径

提高了吞吐率.在SMIC 65 nm的工艺下

吞吐率达到12.68 Gb/s

高于已发表的同类设计.

Abstract

SHA-1 algorithm is one of the national standard for Secure Hash Algorithm. For the sake of accelerating the throughput of SHA-1 algorithm

a new 5-in-1 structure is proposed in this paper. This structure reduces the compression function from original 80 rounds to 16 5-in-1 rounds and in each round some functions f and adders can be moved out of the critical path. Based on this

we can shorten the critical path and increase the throughput. In SMIC 65nm technology

the throughput of SHA-1 can achieve 12.68 Gb/s

which is higher than that of other reported designs and can meet the requirement of high throughput. This design also supports resuming transfer.

关键词

Keywords

references

He J, Chen H, Huang H. A compatible SHA series design based on FPGA[C]//Electrical Engineering/Electronics Computer Telecommunications and Information Technology(ECTI-CON), 2010 International Conference on. Thailand, IEEE, 2010: 380-384.

FIPS. FIPS PUB 180-4. Secure hash standard[S]. USA, the National Instiute of Standards and Technolohgy(NIST), 2015.

Eun Hee Lee, Je Hoon Lee, Ⅱ Hwan Park, et al. Implementation of high -speed SHA-1 architecture[J]. IEICE Electronics Express, 2009, 16(6): 1174-1179. DOI: 1174

William Stallings. 密码编码学与网络安全: 原理与实践[M]. 5版. 北京: 电子工业出版社, 2013.

黄谆, 白国强, 陈弘毅. 快速实现SHA-1算法的硬件结构[J]. 清华大学学报, 2005, 45(1): 123-125. DOI: 123

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