Design of a Current-Steering DAC IP Core Based on 40 nm CMOS Process

WANG Dong; CHEN Lan; FENG Yan

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Design of a Current-Steering DAC IP Core Based on 40 nm CMOS Process

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- Design of a Current-Steering DAC IP Core Based on 40 nm CMOS Process
- Vol. 34, Issue 2, Pages: 25-29(2017)
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 三维及纳米集成电路设计自动化技术北京市重点实验室,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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王东, 陈岚, 冯燕. 一种基于40 nm CMOS工艺的电流舵DAC IP核设计[J]. 微电子学与计算机, 2017, 34(2): 25-29.

WANG Dong, CHEN Lan, FENG Yan. Design of a Current-Steering DAC IP Core Based on 40 nm CMOS Process[J]. 2017, 34(2): 25-29.
王东, 陈岚, 冯燕. 一种基于40 nm CMOS工艺的电流舵DAC IP核设计[J]. 微电子学与计算机, 2017, 34(2): 25-29. DOI：

WANG Dong, CHEN Lan, FENG Yan. Design of a Current-Steering DAC IP Core Based on 40 nm CMOS Process[J]. 2017, 34(2): 25-29. DOI：

摘要

基于SMIC 40 nm CMOS工艺

设计了一种10位100 MS/s DAC IP核.该DAC IP核采用6+4分段式电流舵结构

1.1 V/2.5 V双电源供电

满量程输出电流为20 mA.完成了DAC IP核电路和版图的原型设计

提取了物理模型与时序模型

组成基本的数据交付项.对该DAC IP核进行了仿真分析

给出了流片后的测试结果.

Abstract

Based on SMIC 40 nm CMOS process

a 10 bit 100MS/s DAC IP core was designed. A 6+4 segmented current-steering architecture was employed in the DAC IP core

and the full-scale output current was 20 mA with 1.1 V/2.5 V dual power supplies. For the DAC IP core

the prototype design of circuit and layout was completed

and the physical model and timing model were obtained to form the data deliveries. The simulation analysis of the DAC IP core was carried out

and the test results after tape-out were presented.

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Keywords

references

Yu Chuehao, Chen Wenhui, Li Dayuei, et al. A 1V 10-Bit 400MS/s current-steering D/A converter in 90-nm CMOS[C]//2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). Hsinchu, 2007: 1-4.

Geert A M, Van der Plas, Jan Vandenbussche, Willy Sansen, et al. A 14-bit intrinsic accuracy Q2 random walk CMOS DAC[J]. IEEE Journal of Solid-State Circuits, 1999, 34(12): 1708-1718. DOI: 1708

Yannan Ren, Fule Li, Chun Zhang, et al. A 400MS/s 10-bit current-steering D/A converter[C]//Communications, Circuits and Systems (ICCCAS), 2009 International Conference on. Milpitas, CA, 2009: 533-536.

Zhong Shupeng, Tan Nick. A 12 bit 150 M Sample/s current-steering DAC[C]//Circuits and Systems(APCCAS), 2008 IEEE Asia Pacific Conference on. Macao, 2008: 145-148.

Jurgen Deveugele, Geert Van der Plas, Michiel Steyaert, et al. A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC[J]. IEEE Transactions on Circuits and Systems-Ⅰ: Regular Papers, 2004, 51(1): 191-195. DOI: 191

Luo Min, Yu Mingyan, Li Gen. An 11-Bit high-speed current steering DAC[C]//Consumer Electronics, Communications and Networks (CECNet), 2012 2nd International Conference on. China, Yichang, 2012: 1622-1625.

Cong Yonghua, Randall L Geiger. Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays[J]. IEEE Transactions on Circuits and Systems-Ⅱ: Analog and Digital Signal Processing, 2000, 47(7): 585-595. DOI: 585

王东, 陈岚, 冯燕. 基于40nm CMOS工艺的DAC IP核物理与时序建模[J]. 微电子学与计算机, 2015, 32(2): 56-59. DOI: 56

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