The Analysis of the Stability of 65 nm SRAM at Near Threshold Region

YU Yu-qing; WANG Tian-qi; QI Chun-hua; XIAO Li-yi; YU Pei-fu

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The Analysis of the Stability of 65 nm SRAM at Near Threshold Region

更新时间：2026-09-04

- The Analysis of the Stability of 65 nm SRAM at Near Threshold Region
- Vol. 34, Issue 1, Pages: 26-29(2017)
- 作者机构：
  
  1. 哈尔滨工业大学微电子中心,黑龙江,哈尔滨,150001
  2. 哈尔滨工业大学空间基础科学研究中心,黑龙江,哈尔滨,150001
  3. 哈尔滨工业大学软件学院,黑龙江,哈尔滨,150001
- 作者简介：
- 基金信息：
- DOI：
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- Published：2017
- 稿件说明：
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于雨情, 王天琦, 齐春华, 肖立伊, 喻沛孚. 65 nm近阈值SRAM稳定性分析[J]. 微电子学与计算机, 2017, 34(1): 26-29, 34.

YU Yu-qing, WANG Tian-qi, QI Chun-hua, et al. The Analysis of the Stability of 65 nm SRAM at Near Threshold Region[J]. 2017, 34(1): 26-29.
于雨情, 王天琦, 齐春华, 肖立伊, 喻沛孚. 65 nm近阈值SRAM稳定性分析[J]. 微电子学与计算机, 2017, 34(1): 26-29, 34. DOI：

YU Yu-qing, WANG Tian-qi, QI Chun-hua, et al. The Analysis of the Stability of 65 nm SRAM at Near Threshold Region[J]. 2017, 34(1): 26-29. DOI：

摘要

本文通过将供电电压降低到近阈值区域实现低功耗的目的.现有标准6T-SRAM在近阈值电压下的性能非常差

且受工艺波动的影响很大.因此

本文提出了一种新型的8T-SRAM

与近阈值电压下的6管单元相比

其静态功耗基本相同

读噪声容限也增加了一倍.因此使该新型8管单元在实现低功耗的基础上保证了读写的稳定性.另外针对工艺波动对读噪声容限的影响进行分析

与6T-SRAM相比

新型8T-SRAM受工艺波动的影响更小.

Abstract

Reducing the supply voltage to the near threshold region is one method to reduce the power consumption. However

operating in this region the performance of 6T-SRAM is very poor

and more sensitive to the process variation. In this paper

we introduce a novel 8T-SRAM

when compared to the standard 6T-SRAM

they have the equal static power consumption

and its read noise margin has doubled. So this 8T-SRAM not only has low power consumption

but also has high stability. Further

the impact of process variation on the read noise margin has been analysed

when compared to 6T-SRAM

8T-SRAM is not sensitive to process variation.

关键词

Keywords

references

Reddy G K, Jainwal K, Singh J, et al. Process variation tolerant 9T SRAM bitcell design[C]//Quality Electronic Design (ISQED), 2012 13th International Symposium on. USA, Santa Clara, IEEE, 2012: 493-497.

Madiwalar B, Kariyappa B S. Single bit-line 7T SRAM cell for low power and high SNM[C]//Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), 2013 International Multi-Conference on. India, Kerala, IEEE, 2013: 223-228.

Lim W, Chin H C, Lim C S, et al. Performance evaluation of 14 nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis[J]. Journal of Nanomaterials, 2014: ID: 802736. DOI: 802736

Seevinck E, List F J, Lohstroh J. Static-noise margin analysis of MOS SRAM cells[J]. Solid-State Circuits, IEEE Journal of, 1987, 22(5): 748-754. DOI: 748

Kou L, Robinson W H. Impact of process variations on reliability and performance of 32-nm 6T SRAM at near threshold voltage[C]//VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on. France, Montpellier, IEEE, 2014: 214-219.

Hsieh C Y, Fan M L, Hu V P H, et al. Independently-controlled-gate FinFET Schmitt trigger sub-threshold SRAMs[J]. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2012, 20(7): 1201-1210. DOI: 1201

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