Radiation-Hardened SRAM for Dynamic Voltage Frequency Systems

LI Guang-lin; ZHANG Jie; SHANG Zhong-xia; GENG Li

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Radiation-Hardened SRAM for Dynamic Voltage Frequency Systems

更新时间：2026-09-04

- Radiation-Hardened SRAM for Dynamic Voltage Frequency Systems
- Vol. 34, Issue 4, Pages: 33-38(2017)
- 作者机构：
  
  西安交通大学微电子学院,陕西,西安,710049
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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李广林, 张杰, 商中夏, 耿莉. 适应于动态电压频率调整的抗辐照SRAM设计[J]. 微电子学与计算机, 2017, 34(4): 33-38.

LI Guang-lin, ZHANG Jie, SHANG Zhong-xia, et al. Radiation-Hardened SRAM for Dynamic Voltage Frequency Systems[J]. 2017, 34(4): 33-38.
李广林, 张杰, 商中夏, 耿莉. 适应于动态电压频率调整的抗辐照SRAM设计[J]. 微电子学与计算机, 2017, 34(4): 33-38. DOI：

LI Guang-lin, ZHANG Jie, SHANG Zhong-xia, et al. Radiation-Hardened SRAM for Dynamic Voltage Frequency Systems[J]. 2017, 34(4): 33-38. DOI：

摘要

动态电压频率调整(Dynamic Voltage Frequency Scaling

DVFS)可以使系统在高电压工作时获得高性能

在低电压工作时降低系统功耗

它要求电路能够从正常电压一直到亚阈值区范围内均能正常工作.抗辐照DVFS-SRAM的设计面临着低压工作稳定性及工艺、电压、温度偏差(Process

Voltage

Temperature

PVT)的严重影响.本文针对以上问题

设计了一款适应于DVFS应用的抗辐照静态随机存储器(Static Random Access Memory

SRAM).提出了新型抗辐照DICE单元结构

其读噪声容限相对于原有DICE单元有大幅提升.同时

针对常规分级位线结构时序控制电路存在的问题

提出了改进型复制列技术

增强了SRAM存储体在不同PVT环境下工作的稳定性.对SRAM存储体进行了电路设计及版图设计

后仿真结果表明

设计的512 bit SRAM存储体可在0.6 V~1.8 V电源电压下正常工作.在1.8 V下

SRAM的存取速度为5.1 ns

功耗为1.8 mW; 在0.6 V电压下

SRAM的存取速度为93.5 ns

功耗为14.63 W

比1.8 V电源工作时的功耗降低了约100倍.另外

设计的SRAM对宽度为300 ps以下的单粒子瞬态脉冲具有滤除能力

对单粒子翻转效应有良好的抵抗能力.

Abstract

Dynamic Voltage Frequency Scaling is a method which can not only provide good performance for the system

but also can decrease power consumption. It requires that circuit is able to work in a wide range of supply voltage. However

The design of radiation-hardened SRAM for dynamic voltage frequency systems has faced stability problem because of the process

voltage temperature difference. To cope with these questions

Radiation-Hardened SRAM for dynamic voltage system has been designed. A new DICE cell is proposed for low supply power condition

which has better performance in read static noise margin than the regular DICE cell. In addition

proposed Improved Dummy column has increased the stability of SRAM under various PVT conditions. Post simulation results show that the SRAM circuit can work functionally when the supply voltage changes from 0.6 V to 1.8 V. When the supply voltages are 1.8 V and 0.6 V

the access time of SRAM are 5.1 ns and 93.5 ns

respectively. The power consumption is 1.8 mW and 14.63 W

respectively. The designed SRAM has good immunity for SEU and could filter the SET pulses with width of 300ps.

关键词

Keywords

references

Balasubramanian A, Bhuva B L, Black J D, et al. RHBD techniques for mitigating effects of single-event hits using guard-gates[J]. IEEE Transactions on Nuclear Science, 2006, 52(6): 2531-2535. DOI: 2531

Chang M F, Yang S M, Chen K T, et al. Wide-VDD embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems[J]. IEEE Transactions on Circuits and Systems-Ⅰ, 2009, 56(8): 657-667. DOI: 657

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