This paper presents a dual-mode delta-sigma(ΔΣ)modulator.The modulator can be configured for two structures
3rd-order 4-bit in low-frequency high-resolution applications
and 2nd-order 4-bit in high-frequency lowresolution applications.Most of the circuit parts including the capacitors and switches are shared in both modes.An efficient OTA and comparators with Input Offset Calibration(IOS)technique are adopted.The modulator is fabricated in0.18m CMOS technology.It achieves 77.1dB and 108.9dB peak signal-to-noise and distortion ratio(SNDR)separately in two modes with 39 kHz and 1.25 MHz input signal bandwidth.The power consumption is about 12 mW.
关键词
Keywords
references
Dessouky M, Kaiser A. A 1V1mW digital-audio ΔΣ modulator with 88dB dynamic range using local switch bootstrapping[C]//2000IEEE Custom Integrated Circuits Conference. San Jose, 2000: 13-16.
Lim J. A low-power sigma-delta modulator for wireless communication receivers using adaptive biasing circuitry and cascaded comparator scheme[C]//Analog Integrated Circuits and Signal Processing. Berlin, Springer, 2006: 359-365.
Miller T M R. A multibit sigma-delta ADC for multimode receivers[C]//IEEE J. of Solid-State Circuits. San Franceise, 2003: 475-482.
Gaggl R, Inversi M, Wiesbauer A. A power optimized14-bit SC ΔΣ modulator for ADSL CO applications[C]//IEEE International Solid-State Circuits Conference, San Francisco, 2004: 82-83.
Malla P, Lakdawala H, Kornegay K. A 28mW SpectrumSensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMax Receivers[C]//IEEE International Solid-State Circuits Conference. San Francisco, 2008.
Yin G, Eynde F, Sansen W. A high-speed CMOS comparator with 8-b resolution[J]. IEEE Journal of SolidState Circuits, 1992, 27(2): 208-211. DOI: 208
Fujimoto Y, Kanazawa Y, Lore P, et al. An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for digital TV receivers[C]//IEEE International Solid-State Circuits Conference. San Francisco, 2006: 76-77.
Christen T. A 0.13μm CMOS EDGE/UMTS/WLAN Tri-ModeΣΔADC with-92dB THD[C]//Proc. ISSCC 2007. San Francise, 2007: 240-241.
Yi K, Soheil R, Jan C, et al. A systematic design methodology for power-optimal design of high-order multi-bit continuous-time Delta-Sigma modulators[C]//Springer Analog Integrated Circuits and Signal Processing. Berlin, Springer, 2008.