A Buffer Layer Design in Serial RapidIO

REN Xue-qian; LI Jin-cheng; ZHAO Jian-zhong; ZHANG Feng

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A Buffer Layer Design in Serial RapidIO

更新时间：2026-09-04

- A Buffer Layer Design in Serial RapidIO
- Vol. 33, Issue 9, Pages: 47-50(2016)
- 作者机构：
  
  1. 中国科学院机构微电子研究所智能感知研发中心,北京,100029
  2. 北京交通大学电子信息工程学院,北京,100044
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
- 稿件说明：
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任雪倩, 李金城, 赵建中, 张锋. 基于串行RapidIO的Buffer层设计[J]. 微电子学与计算机, 2016, 33(9): 47-50.

REN Xue-qian, LI Jin-cheng, ZHAO Jian-zhong, et al. A Buffer Layer Design in Serial RapidIO[J]. 2016, 33(9): 47-50.
任雪倩, 李金城, 赵建中, 张锋. 基于串行RapidIO的Buffer层设计[J]. 微电子学与计算机, 2016, 33(9): 47-50. DOI：

REN Xue-qian, LI Jin-cheng, ZHAO Jian-zhong, et al. A Buffer Layer Design in Serial RapidIO[J]. 2016, 33(9): 47-50. DOI：

摘要

RapidIO是一种新兴的高性能互联总线

主要应用于嵌入式系统.作为串行RapidIO结构的重要组成部分

Buffer层负责保证数据包的可靠传输

并且在链路级流量控制中起着重要作用.对此提出了一种改进的buffer层结构

同时支持发送端流量控制和接收端流量控制两种模式.仿真结果表明

该buffer层有效地提高了buffer的空间利用率和传输效率.该设计在高性能嵌入式系统中具有一定的工程应用价值.

Abstract

RapidIO is an emerging high-performance interconnect technology for embedded system interconnection. As a very significant part of serial RapidIO

buffer layer helps to guarantee reliable packet delivery and plays an important role in link level flow control. In this paper

the design of an improved buffer layer in serial RapidIO endpoint is described in detail. Both transmitter-controlled flow control and receiver-controlled flow control are supported in this design. Simulation results show that the proposed buffer layer has better space utilization and higher transmission efficiency

compared with the referenced designs. It is valuable for high performance embedded system applications to some extent.

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references

Xilinx. LogiCORE IP serial rapidIO Gen2 endpoint v2.0. product guide for vivado Design Suite[R]. 2013.

Wu Fengfeng, Jia Song, Wang Yuan. An effective buffer space management in serial rapidIO endpoint[C]//2011 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. Macaa: IEEE, 2011: 135-138.

UK Sam Fuller. RapidIO: The embedded system interconnect[M]. UK: John Wiley % Sons, 2005.

David Bueno, Adam Leko, Chris Conger, et al. Simulative analysis of the rapidIO embedded interconnect architecture for real-time, network-intensive applications[C]//Proceedings of the 29th Annual IEEE International Conference on Local Computer Networks. Tampa, FL, USA: IEEE, 2004: 710-727.

X B Zhao, S Jia, Y Wang, et al. Buffer design based on flow control in rapidIO[C]//2010 Asia Pacific conference on Postgradvate Research in Microelectronics and Electronics. Shanghai: IEEE, 2010: 150-153.

The RapidIO trade association. RapidIO interconnect specification part6[S]. Rev 2.1. 2009.

Syed Ijlal Ali Shah, Shashank Khanvilkar, Ashfaq Khokhar. RapidIO traffic management and flow arbitration protocol[J]. IEEE Communications Magazine, 2006, 44(7) : 45-51. DOI: 45

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