An All-Digital Clock Generator Using Relative Delay Ratio Modeling

SUN Ya-peng; XIE Zheng-zhang; ZHAO Hui-dong; QIAO Shu-shan; HEI Yong; ZHANG Fu-hai

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An All-Digital Clock Generator Using Relative Delay Ratio Modeling

更新时间：2026-09-04

- An All-Digital Clock Generator Using Relative Delay Ratio Modeling
- Vol. 34, Issue 6, Pages: 49-53(2017)
- 作者机构：
  
  1. 南开大学电子信息与光学工程学院,天津,300350
  2. 中国科学院机构微电子研究所,北京,100029
  3. 中国科学院大学机构,北京,101408
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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孙雅芃, 谢正章, 赵慧冬, 乔树山, 黑勇, 张福海. 一种基于相对延时比模型的全数字时钟电路产生器[J]. 微电子学与计算机, 2017, 34(6): 49-53.

SUN Ya-peng, XIE Zheng-zhang, ZHAO Hui-dong, et al. An All-Digital Clock Generator Using Relative Delay Ratio Modeling[J]. 2017, 34(6): 49-53.
孙雅芃, 谢正章, 赵慧冬, 乔树山, 黑勇, 张福海. 一种基于相对延时比模型的全数字时钟电路产生器[J]. 微电子学与计算机, 2017, 34(6): 49-53. DOI：

SUN Ya-peng, XIE Zheng-zhang, ZHAO Hui-dong, et al. An All-Digital Clock Generator Using Relative Delay Ratio Modeling[J]. 2017, 34(6): 49-53. DOI：

摘要

设计了一种应用于低功耗领域的基于相对延时比模型的全数字时钟生成器

解决了环形振荡器产生振荡周期受到工艺偏差、环境温度偏移和供电电压抖动等因素影响的问题.该时钟生成器由相对延时比生成器、映射译码单元和数字控制振荡器组成.一款10~40 MHz频率可调节的全数字时钟电路生成器基于smic180 nm CMOS工艺库

整个芯片面积(除IO pad)为1.02 mm.测试结果表明

当目标频率设定为25 MHz

在供电电压在1.6~2 V

环境温度在0~80℃变化时

该时钟生成器的最大输出频率误差为3%

输出时钟相位噪声在1 MHz频偏处为-114.82 dBc/Hz

具有良好的频率稳定性.

Abstract

Using the relative delay ratio modeling

an all-digital clock generator which is used for low power applications is proposed. It overcomes the effects of process

voltage and temperature (PVT) variations. The clock generator is composed of delay ratio evaluator

mapper block and digitally controlled oscillator. A 10~40MHz adjustable clock generator is implemented in smic 180nm CMOS technology with 1.02mm (excluding IO pad). The measured results show that the worst output frequency error is less than 3% at 25MHz

with 1.6~2V supply voltage

0~80℃ temperature variation. The phase noise of output clock is -114.82dBc/Hz at 1MHz offset with high stability performance.

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references

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