A 12-Bit 60 MHz Pipeline ADC Based on 40 nm CMOS Process

XIE Can; WEI Zi-hui; HUANG Shui-long

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A 12-Bit 60 MHz Pipeline ADC Based on 40 nm CMOS Process

更新时间：2026-09-04

- A 12-Bit 60 MHz Pipeline ADC Based on 40 nm CMOS Process
- Vol. 33, Issue 11, Pages: 54-59(2016)
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 新一代通信射频芯片技术北京市重点实验室,北京,100029
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
- 稿件说明：
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谢灿, 魏子辉, 黄水龙. 一种基于40 nm CMOS工艺12位60 MHz流水线模数转换器[J]. 微电子学与计算机, 2016, 33(11): 54-59.

XIE Can, WEI Zi-hui, HUANG Shui-long. A 12-Bit 60 MHz Pipeline ADC Based on 40 nm CMOS Process[J]. 2016, 33(11): 54-59.
谢灿, 魏子辉, 黄水龙. 一种基于40 nm CMOS工艺12位60 MHz流水线模数转换器[J]. 微电子学与计算机, 2016, 33(11): 54-59. DOI：

XIE Can, WEI Zi-hui, HUANG Shui-long. A 12-Bit 60 MHz Pipeline ADC Based on 40 nm CMOS Process[J]. 2016, 33(11): 54-59. DOI：

摘要

采用带采样/保持电路

由10级1.5位每级级电路和最后一级为2位flash ADC组成的流水线结构

设计了一种12位60 MHz高性能流水线模数转换器.在设计中采用栅压自举开关降低非线性

采用带增益自举的折叠式共源共栅输入级和AB类输出级的运放

采用动态锁存比较器

同时逐级优化级电路中采样电容以及运放的增益和带宽.在SMIC 40 nm CMOS工艺下

当输入信号为1.875 MHz

采样速率为60 MHz时

SNDR为68.7 dB

SFDR为74.6 dB

ENOB为11.12 bit

芯片的核心面积为0.95 mm

1.1 V的电源电压下

消耗的总电流为56 mA.

Abstract

A 12-bit 60 MHz high-performance pipeline ADC is designed in this paper

which consists of sample/hold circuit

1.5-bit/stage conversion circuit applied from 1 to 10 and a 2-bit flash ADC of the last stage. In this design a gate-bootstrapping switch was used to reduce nonlinear

an operational amplifier with a gain-boosting folded cascade input stage and a class AB output stage was used

dynamic latch comparator was used too

meanwhile

optimizing the sampling capacitor

the gain and bandwidth of the operational amplifier in the circuit stage by stage. In a SMIC 40 nm CMOS process

when the input signal frequency was 1.875 MHz and the sampling frequency was 60 MHz

the SNDR was 68.7 dB

the SFDR was 74.6 dB

the ENOB was 11.12 bits

the core area of chip was 0.95 mm

the total dissipation current was 56 mA under the 1.1 V supply voltage.

关键词

Keywords

references

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尹睿. 高精度、低功耗流水线型模数转换器的研究与设计[D]. 上海: 复旦大学, 2010.

Panigada A, Galton I. A 130mW 100MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction[J]. IEEE J Solid-State Circuits, 2009, 44(12): 3314-3328. DOI: 3314

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景鑫, 庄奕琪, 汤华莲, 等. 采用改进自举开关的12 bit 40MS/s流水线ADC[J]. 华中科技大学学报(自然科学版), 2013, 41(8): 30-33. DOI: 30

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