Design of a Full Load Stability High-PSRR Low Dropout Regulator

ZHANG Long; LAI Qiang-tao; LIU Sheng-you; GUO Gui-liang; DAI Yu-jie

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Design of a Full Load Stability High-PSRR Low Dropout Regulator

更新时间：2026-09-04

- Design of a Full Load Stability High-PSRR Low Dropout Regulator
- Vol. 34, Issue 2, Pages: 58-62(2017)
- 作者机构：
  
  1. 南开大学电子信息与光学工程学院,天津,300071
  2. 中国科学院机构微电子研究所,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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张龙, 来强涛, 刘生有, 郭桂良, 戴宇杰. 一种全负载稳定的高PSRR LDO的设计[J]. 微电子学与计算机, 2017, 34(2): 58-62.

ZHANG Long, LAI Qiang-tao, LIU Sheng-you, et al. Design of a Full Load Stability High-PSRR Low Dropout Regulator[J]. 2017, 34(2): 58-62.
张龙, 来强涛, 刘生有, 郭桂良, 戴宇杰. 一种全负载稳定的高PSRR LDO的设计[J]. 微电子学与计算机, 2017, 34(2): 58-62. DOI：

ZHANG Long, LAI Qiang-tao, LIU Sheng-you, et al. Design of a Full Load Stability High-PSRR Low Dropout Regulator[J]. 2017, 34(2): 58-62. DOI：

摘要

提出了一种高电源纹波抑制比的低压差线性稳压器.该低压差线性稳压器通过提高带隙基准的电源抑制比以达到提高LDO(低压差线性稳压器)低频电源纹波抑制的能力.在TSMC 0.18μm CMOS工艺下进行了仿真验证

仿真结果表明

该LDO最大负载电流可以达到80 mA

当负载电流在0~80 mA范围内变化时

开环相位裕度均大于64°

证明了低压差线性稳压器的高稳定性.当负载电流从0 mA跳变到80 mA时

系统的输出电压过冲仅为15 mV

环路响应时间仅为0.5 μs.当负载电流为80 mA

测得10 kHz时的电源纹波抑制比为-60.82 dB

100 kHz时LDO的电源纹波抑制比为-57.66 dB.

Abstract

An improved power supply ripple rejection (PSRR) low drop-out (LDO) voltage regulator circuit is proposed. The LDO improves the ability of power supply ripple rejection ratio by improving power supply rejection ratio of the bandgap reference. This approach is tested in TSMC 0.18 μm COMS process. The results show that the maximum load current is 80 mA

and the open-loop phase margin is not less than 64° at a load current from 0 to 80 mA which proves the high stability of LDO. In addition

the circuit achieves a transient response with 15 mV voltage variation and 0.5 μs settling time for an 80 mA load step. The PSRR at 10 kHz is -60.82 dB and 100kHz is 57.66 dB.

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references

Heng S, Pham C K. A low-power high-PSRR low-dropout regulator with bulk-gate controlled circuit[J]. IEEE Trans Circ Syst, 2010, 57(4): 868-873. DOI: 868

Hoon S, Chen J, Maloberti F, et al. An improved bandgap reference with high power rejection[J]. IEEE Int. Symp. Circuits and Systems (ISCAS), 2002, 5(6): 833-836. DOI: 833

EL-Nozahim, Amer A, Torres J, et al. High PSR low drop-out regulator with feed-forward ripple cancellation technique[J]. IEEE Journal of Solid-state Circuits, 2010, 45 (3): 565-577. DOI: 565

Gupta V, Rincon M G. A 5 mA 0.6 μm CMOS Miller compensated LDO regulator with -27dB worst-case power-supply rejection using 60 pF of on-chip capacitance[C]// IEEE International Solid-state Circuits Conference (ISSCC). San Francisco, CA, USA: IEEE Press, 2007: 520-521.

杨洁, 曾云. 一种快速瞬态响应的无片外电容LDO的设计[J]. 微电子学与计算机, 2012, 29(8): 124-126. DOI: 124

吴勤, 李巍, 李宁, 等. 一种提高电源抑制率的线性稳压器设计[J]. 微电子学与计算机, 2012, 29(6): 735-739. DOI: 735

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