In this paper it proposes a high performance 14-bit 200 Ms/s current-steering DAC. It analyses the non-ideal factors and models the proposal DAC based on Verilog-A

adopts a swing limited circuit to process the control signal of current source switches

and introduces a split and symmetrical layout of current sources scheme to reduce the process error in fabrication. At last

it is fabricated with SMIC 0.18 m Mixed-Signal CMOS technology. With 3.3 V/1.8 V power supply

the SFDR in the post simulation results of this DAC are 100.1 dB and 88.3 dB respectively under the condition of 1 MHz and 20 MHz input signal and 200 MHz sample clock.