Design of One Kind of Channel Interleaver/Deinterleaver in the Carrier Communication SOC

DAI Lan; ZHANG Yang

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Design of One Kind of Channel Interleaver/Deinterleaver in the Carrier Communication SOC

更新时间：2026-09-04

- Design of One Kind of Channel Interleaver/Deinterleaver in the Carrier Communication SOC
- Vol. 34, Issue 5, Pages: 59-62(2017)
- 作者机构：
  
  北方工业大学机构微电子系,北京,100144
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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戴澜, 张扬. 一种载波通信SOC信道交织/解交织器设计[J]. 微电子学与计算机, 2017, 34(5): 59-62.

DAI Lan, ZHANG Yang. Design of One Kind of Channel Interleaver/Deinterleaver in the Carrier Communication SOC[J]. 2017, 34(5): 59-62.
戴澜, 张扬. 一种载波通信SOC信道交织/解交织器设计[J]. 微电子学与计算机, 2017, 34(5): 59-62. DOI：

DAI Lan, ZHANG Yang. Design of One Kind of Channel Interleaver/Deinterleaver in the Carrier Communication SOC[J]. 2017, 34(5): 59-62. DOI：

摘要

基于HomePlug AV协议设计了一款在电力线载波通信SOC芯片中得到广泛应用的信道交织/解交织器

通过设置不同的文件顶层配置参数

可以使交织/解交织器以半双工方式工作在芯片中.该设计通过算法实现、寄存器级(RTL)设计并进行ModelSim和Synopsys仿真及DC综合后仿

成功地证明了设计的正确性.在100 MHz工作频率下运用DC综合工具进行时序时序分析可以得知

slack (MET)为2.45

面积为22 702.048 020 μm

功耗为658.043 4 μW.

Abstract

On the basis of HomePlug AV socket protocol

designed a kind of Channel interleaver/deinterleaver is designed which can apply in the power line carrier communication SOC chip. By setting the top configuration parameters for different files

we can get the half duplex mode working of channel interleaver/deinterleaver in the chip. Through the algorithm and RTL design and ModelSim subsequent Synopsys composite tools DC comprehensive simulation

verify the correctness of the design. The timing results show that at 100 MHz clock

slack(MET) is 2.45

the total cell area: is 22 702.048 020 μm

and the power estimation results are 658.043 4 μW.

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references

HomePlug Powerline Alliance. HomePlug AV Specification Version 1.0.10[M]. HomePlug, 2007.

史治国, 洪少华, 陈抗生. 基于XILINX FPGA的OFDM通信系统基带设计[M]. 杭州: 浙江大学出版社, 2009.

Jan M Rabaey, Anantha Chandrakasan, Borivoje Nikolic. 数字集成电路——电路、系统与设计[M]. 周润德, 译. 北京: 电子工业出版社, 2012.

IEEE. IEEE standard for broadband over power line networks: medium access control and physical layer specifications, IEEE Std 1901TM-2010[S]. IEEE, 2010.

Michael D Ciletti. Verilog HDL高级数字设计[M]. 李广军, 林水生, 阎波, 等译. 北京: 电子工业出版社, 2014.

Himanshu Bhatnagar. 高级ASIC芯片综合[M]. 张文俊, 译. 北京: 清华大学出版社, 2007.

张利平, 魏巍. 宽带载波电力线通信协议中信道交织的FPGA实现[J]. 电子技术, 2015, 28(9): 74-76. DOI: 74

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