Design of a Pipelined SAR ADC Used in CMOS Image Sensor

LI Zhen; LI Dong-mei

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Design of a Pipelined SAR ADC Used in CMOS Image Sensor

更新时间：2026-09-04

- Design of a Pipelined SAR ADC Used in CMOS Image Sensor
- Vol. 33, Issue 11, Pages: 64-68(2016)
- 作者机构：
  
  清华大学电子工程系,北京,100084
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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李臻, 李冬梅. 应用于CMOS图像传感器的Pipelined SAR模数转换器设计[J]. 微电子学与计算机, 2016, 33(11): 64-68.

LI Zhen, LI Dong-mei. Design of a Pipelined SAR ADC Used in CMOS Image Sensor[J]. 2016, 33(11): 64-68.
李臻, 李冬梅. 应用于CMOS图像传感器的Pipelined SAR模数转换器设计[J]. 微电子学与计算机, 2016, 33(11): 64-68. DOI：

LI Zhen, LI Dong-mei. Design of a Pipelined SAR ADC Used in CMOS Image Sensor[J]. 2016, 33(11): 64-68. DOI：

摘要

设计实现一种应用于CMOS图像传感器的10 bit模数转换器(ADC)

采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态比较器等技术提高了整体电路的线性度

并降低了系统功耗.通过对版图面积的优化设计

满足了CMOS图像传感器对芯片面积的要求.本设计基于180 nm CMOS工艺

仿真结果显示电路实现了60.37 dB的信噪失真比(SNDR)和76.37 dB的无杂散动态范围(SFDR)

有效精度(ENOB)达到了9.74 bit.ADC的核心面积仅为140 mⅹ280 m

约为0.04 mm.在2.8 V电压下

功耗为9.8 mW.

Abstract

This paper presents a novel architecture to achieve a 10 bit pipeline ADC based on SAR technique which is used in a CMOS image sensor. A theoretical analysis is proposed to determine the high resolution MDAC and the suitable value of unit capacitor. The high-resolution first stage

the half-gain MDAC and the dynamic comparator are adopted to improve the linearity and to reduce the power. To satisfy the strict area requirement of CMOS image sensor

the layout is carefully designed. This pipelined SAR ADC is designed and fabricated in SMIC 180 nm CMOS technology. Simulation results show the ADC achieves 60.37 dB signal to noise distortion ratio (SNDR) and 76.37 dB spurious free dynamic range(SFDR). The effective number of bits (ENOB) achieves 9.74 bit. The core area is 140 m×280 m

about 0.04 mm. The power dissipation is 9.8 mW in typical case under 2.8 V supply.

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references

Xue F, Wei X, Hu Y, et al. Design of a 10-bit 50MSPS pipeline ADC for CMOS image sensor[C]// Industrial Electronics and Applications (ICIEA), 2014 IEEE 9th Conference on. [s. l. ]: IEEE, 2014: 891-895.

Lee B G, Min B M, Manganaro G, et al. A 14b 100MS/s pipelined ADC with a merged active S/H and first MDAC[C]//Solid-State Circuits Conference, Digest of Technical Papers IEEE International. Boston: IEEE, 2012: 248-611.

李臻. CMOS图像传感器中的10位Pipelined SAR ADC研究与设计[D]. 北京: 清华大学, 2016.

Wang Q, Zhou L, Peng Z, et al. A 12-b 100MS/s low-power successive approximation register ADC in 65 nm COMS[C]// Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on. BerLin: IEEE, 2004: 1-2.

Chan C H, Zhu Y, Chio U, et al. A reconfigurable low-noise dynamic comparator with offset calibration in 90 nm CMOS[C]// Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian. IEEE, 2011: 233-236.

Yang W, Kelly D, Mehr I, et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input[J]. Solid-State Circuits, IEEE Journal of, 2010, 36(12): 1931-1936. DOI: 1931

Lee C C, Flynn M P. A SAR-assisted two-stage pipeline ADC[J]. Solid-State Circuits, IEEE Journal of, 2011, 46(4): 859-869. DOI: 859

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