Parallel Correction Unit of Leading Digitals Design and Simulation

WEI Si-jie; FU Kun; YUAN Yu-qian; GENG Yue-hua

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Parallel Correction Unit of Leading Digitals Design and Simulation

更新时间：2026-09-04

- Parallel Correction Unit of Leading Digitals Design and Simulation
- Vol. 34, Issue 5, Pages: 67-72(2017)
- 作者机构：
  
  1. 河北工业大学计算机科学与软件学院,天津,300401
  2. 河北省大数据计算重点实验室,天津,300401
  3. 河北工业大学电气工程学院,天津,300401
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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魏思捷, 富坤, 袁玉倩, 耿跃华. 前导数字并行纠错单元的设计与仿真[J]. 微电子学与计算机, 2017, 34(5): 67-72.

WEI Si-jie, FU Kun, YUAN Yu-qian, et al. Parallel Correction Unit of Leading Digitals Design and Simulation[J]. 2017, 34(5): 67-72.
魏思捷, 富坤, 袁玉倩, 耿跃华. 前导数字并行纠错单元的设计与仿真[J]. 微电子学与计算机, 2017, 34(5): 67-72. DOI：

WEI Si-jie, FU Kun, YUAN Yu-qian, et al. Parallel Correction Unit of Leading Digitals Design and Simulation[J]. 2017, 34(5): 67-72. DOI：

摘要

对前导数字预测算法的误差修正逻辑进行分析改进和设计实现

重点对该误差修正纠错模块的逻辑设计进行了分析证明

依据设计的逻辑表达式对其电路进行了设计.同时采用硬件描述语言VerilogHDL编程

结果使用QuartusⅡ进行仿真验证.使用性能分析软件对提出的纠错逻辑方案进行验证

可以看出本纠错单元的电路在电路面积和功耗上都有明显的改善.

Abstract

In this paper

we put forward a novel design of the error correction logic.At the same time

we also design the circuit and programed it with QuartusⅡ.At the end of the article we also give the verification and simulation results. The results of the performance analysis tools show that the error correction circuit we put forward in this article improved significantly in the circuit area and the power.

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references

Yao Tao, Gao Deyuan. A novel concurrent error detection circuit for leading zero anticipator[C]//Proc. of 2nd International Conference on Computer Engineering and Technology(ICCET), 2010. IEEE, 2010.

Zhang Ge, Qi Zichu, Hu Weiwu. Anovel design of leading zero anticipation circuit with parallel error diction[C]//IEEE International Symposium on Circuits and Systems. IEEE, 2005.

Javier D Bruguera, Tomas Lang. Leading-one prediction with concurrent position correction[J]. IEEE Transcations Computers, 1999, 48(10): 1083-1097. DOI: 1083

Kershaw R, Bays L, Freyman R, et al. A programmable digital signal processor with 32-bit floating-point arithmetic[C]//IEEE Solid Circuits Conference, Digest of Papers. IEEE, 1985.

Suzuki H, Morinaka H, Makino H, et al. Leading-zero anticipatory logic for high-speed floating point addition[J]. IEEE Journal of Solid State Circuits, 1996, 31(8): 1157-1164. DOI: 1157

Hays W, Kershaw R, Bays L, et al. A 32-bit VLSI digital signal processor[J]. IEEE Journal of Solid State Circuits, 1985, SC-20(5): 998-1004. DOI: 998

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