Design of Floating Point Number Generator Based on High-Efficiency Constraint Solving Algorithm

HU Guang-yin; WANG Zi-ou; WU Sheng-guang; WANG Shen-zhuo

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Design of Floating Point Number Generator Based on High-Efficiency Constraint Solving Algorithm

更新时间：2026-09-04

- Design of Floating Point Number Generator Based on High-Efficiency Constraint Solving Algorithm
- Vol. 33, Issue 11, Pages: 78-82(2016)
- 作者机构：
  
  苏州大学电子信息学院,江苏,苏州,215000
- 作者简介：
- 基金信息：
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- Published：2016
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胡广垠, 王子欧, 吴升光, 王申卓. 基于高效约束解决算法的浮点数生成器设计[J]. 微电子学与计算机, 2016, 33(11): 78-82, 86.

HU Guang-yin, WANG Zi-ou, WU Sheng-guang, et al. Design of Floating Point Number Generator Based on High-Efficiency Constraint Solving Algorithm[J]. 2016, 33(11): 78-82.
胡广垠, 王子欧, 吴升光, 王申卓. 基于高效约束解决算法的浮点数生成器设计[J]. 微电子学与计算机, 2016, 33(11): 78-82, 86. DOI：

HU Guang-yin, WANG Zi-ou, WU Sheng-guang, et al. Design of Floating Point Number Generator Based on High-Efficiency Constraint Solving Algorithm[J]. 2016, 33(11): 78-82. DOI：

摘要

为了对微处理器中浮点运算单元FPU(floating-point unit)进行高效的功能验证

对浮点运算的边界情况进行了研究

引入了对中间结果(intermediate result)的约束解决算法(constriant solved arithmetic).与传统的对浮点运算单元的功能验证相比

基于该约束算法的浮点数生成器

拓宽了浮点边界情况的可选范围

有效提高了验证效率.实验结果表明

集成该浮点数生成器的UVM验证平台

能够在12小时的测试时间内

对一个浮点运算子模块(floating-point subunit)达到超过99%的覆盖率.

Abstract

In order to verify the function of the floating-point unit in the microprocessor high-efficiently

numerous corner cases of floating-point arithmetic has been studied. Several arithmetics are introduced to solve the constriants of the intermediate results. Compared with the traditional function verification of floating-point unit

the floating-point number generator based on the constraint solved algorithms has widened the scope of the optional floating-point corner cases

which effectively improves the verification efficiency.Experimental results show that the UVM verification platform which integrated the generator can test one floating-point subunit efficiently

which achieves high coverage beyond 98%

within 12 hours of testing time.

关键词

Keywords

references

Goni O, Todorovich E. Components for Coverage-Driven Verification of floating-point units[C]// IX Southern Conference on Programmable Logic (SPL). Montpellier, France: IEEE, 2014: 1-7.

AAR Sayed-Ahmed. Three engines to solve verification constraints of decimal Floating-Point operation[C]// Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR). Nontpellier, France: IEEE, 2010: 1153-1157.

M. Aharoni. Solving Constraints on the Intermediate Result of Decimal Floating-Point Operations[C]//Proc 18th IEEE Computer Arithmetic Symp. Santiago: IEEE, 2007: 38-45.

Ziv A. Solving the generalized mask constraint for test generation of binary floating point add operation[J]. Theoretical Computer Science, 2003, 291(2): 183-201. DOI: 183

于伽. 随机测试程序发生器的设计与实现[J]. 微电子学与计算机, 2012, 29(7): 103-106. DOI: 103

陈博文. 浮点乘加部件的自动化形式验证[J]. 计算机研究与发展, 2010, 47(S1): 262-267. DOI: 262

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Related Institution

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