14 Bits 200MSPS Digital Self-Calibration Current-Steering D/A Converter

DAI Lan; ZHANG Yang; SUN Hai-yan

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14 Bits 200MSPS Digital Self-Calibration Current-Steering D/A Converter

更新时间：2026-09-04

- 14 Bits 200MSPS Digital Self-Calibration Current-Steering D/A Converter
- Vol. 34, Issue 4, Pages: 94-97(2017)
- 作者机构：
  
  北方工业大学机构电子信息工程学院微电子系,北京,100144
- 作者简介：
- 基金信息：
- DOI：
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- Published：2017
- 稿件说明：
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戴澜, 张扬, 孙海燕. 14-bit 200MS/s数字自校准电流舵式D/A转换器[J]. 微电子学与计算机, 2017, 34(4): 94-97.

DAI Lan, ZHANG Yang, SUN Hai-yan. 14 Bits 200MSPS Digital Self-Calibration Current-Steering D/A Converter[J]. 2017, 34(4): 94-97.
戴澜, 张扬, 孙海燕. 14-bit 200MS/s数字自校准电流舵式D/A转换器[J]. 微电子学与计算机, 2017, 34(4): 94-97. DOI：

DAI Lan, ZHANG Yang, SUN Hai-yan. 14 Bits 200MSPS Digital Self-Calibration Current-Steering D/A Converter[J]. 2017, 34(4): 94-97. DOI：

摘要

采用一种新型数字校准算法

改变了传统方法对电流源单元总是从最低位地址选取的方法

通过对电流源单元选取起点和终点的计算和存储

对电流源单元采用"选取方向随机"和特殊代码全随机选取的办法

将电流源的失配转换为白噪声并有效提高了DAC的动态性能.在采用SMIC18 1P6M工艺的情况下获得的后仿真结果表明

相对于不加校准的设计

SFDR从88.3 dB提高到92.3 dB

而总体芯片面积不变.

Abstract

In this paper it adopted a novel a digital calibration algorithm

and it selects the current sources with random ways which keeps to the principles of random selection direction and full random selection on the situation of special code through calculating and storing the starting and finishing point

by this way it can whiten the mismatch noise and improve dynamic performance of DAC. Based on SMIC18 1P6M technology

a 14 bits 200MSPS digital self-calibration current-Steering DAC is implemented and its post simulation results show the SFDR is improved from 88.3 dB to 92.3 dB with calibration but the area of this chip is similar to the non-calibration one.

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Keywords

references

Tseng Wei-Hsin, Fan Chi-Wei, Wu Jieh-Tsorng. A 12b 1.25GS/s DAC in 90nm CMOS with > 70 dB SFDR up to 500 MHz[J]. J. Solid-State Circuits, 2011, 46, (12): 2845-2856. DOI: 2845

Zhao Jinchen, Wu Xiaobo, Zhao Menglian. A digital front-end of 16-bit audio delta-sigma DAC with improved CSE method and novel DWA[C]// IEEE International on New Circuits and Systems Conference (NEWCAS). IEEE, 2012 : 273-276.

Tao Zeng, Townsend K, Duan Jingbo, et al. A 15-bit binary-weighted current-steering DAC with ordered element matching[C]// IEEE Custom Integrated Circuits Conference. IEEE, 2013: 1-4.

Shen M H, Tsai J H, Huang P C. Random swapping dynamic element matching technique for glitch energy minimization in current-steering DAC[J]. Circuits % Systems Ⅱ Express Briefs IEEE Transactions on, 2010, 57(5): 369-373. DOI: 369

王向展, 宁宁, 徐振涛, 等. 一种14位400 MS/s分段型电流舵DAC的设计[J]. 微电子学, 2011, 41(2): 199-202. DOI: 199

Li X, Wei Q, Xu Z, et al. A 14 bit 500 MS/s CMOS DAC using complementary switched current sources and time-relaxed interleaving DRRZ[J]. Circuits % Systems I Regular Papers IEEE Transactions on, 2014, 61(8): 2337-2347. DOI: 2337

Xu Zhen, Li Xueqing, Liu Jiannan, et al. A 14-bit 500-MS/s DAC with digital background calibration[J]. Journal of Semiconductors, 2014, 35(3): 035008.1-035008.6. DOI: 035008.1

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