Verification of Floating Point Facilities Based on UVM

WU Sheng-guang; YANG Jian-feng; FENG Chun-yang

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Verification of Floating Point Facilities Based on UVM

更新时间：2026-09-04

- Verification of Floating Point Facilities Based on UVM
- Vol. 34, Issue 4, Pages: 121-125(2017)
- 作者机构：
  
  1. 苏州大学电子信息学院,江苏,苏州,215021
  2. 中晟宏芯有限公司,江苏,苏州,215000
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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吴升光, 羊箭锋, 冯春阳. 基于UVM的浮点功能部件验证[J]. 微电子学与计算机, 2017, 34(4): 121-125, 130.

WU Sheng-guang, YANG Jian-feng, FENG Chun-yang. Verification of Floating Point Facilities Based on UVM[J]. 2017, 34(4): 121-125.
吴升光, 羊箭锋, 冯春阳. 基于UVM的浮点功能部件验证[J]. 微电子学与计算机, 2017, 34(4): 121-125, 130. DOI：

WU Sheng-guang, YANG Jian-feng, FENG Chun-yang. Verification of Floating Point Facilities Based on UVM[J]. 2017, 34(4): 121-125. DOI：

摘要

为了对复杂浮点运算单元进行功能验证

设计并实现了一种基于UVM (Universal Verification Methodology)方法的验证平台.该平台集成了一套高效的浮点数产生机制

将浮点用例的求解转化为连分式的求解

拓宽了传统浮点用例的边界定义

同时也调用了基于C语言的参考模型来自检计算结果

并结合FCC (Fast Coverage Convergence)技术

加快了覆盖率收敛.应用结果表明

此验证平台能够对浮点运算单元各功能进行高效验证

极大地减少验证时间

且平台内嵌的浮点数产生器也能够移植到其他浮点功能验证平台.

Abstract

A test-bench was designed and implemented on the basis of UVM to verify all facilities of the floating-point unit. The test-bench integrates an efficient mechanism to generate floating-point operands and expands the corner of traditional cases with the method of convert floating point numbers to continued fractions. It calls a C model to achieve automatic results comparison

in addition to FCC technique

the coverage was converged quickly. Experimental results show that the test-bench can effectively verify all facilities of the floating-point unit and greatly reduce the time

moreover

the floating-point generator can be used for other floating-point verification.

关键词

Keywords

references

Ziv A. Solving range constraintsfor binary floating-point instructions[C]//Proc. 16th IEEESymposium on Computer Arithmetic (ARITH16). IEEE, 2003: 158-164.

New York Khinchin A Y. Continued fractions[M]. New York: Dover, 1997: 105-126. DOI: 105

Wazlowski M E, Adiga N R, et al. Verification strategy for the Blue Gene/L chip[J]. IBM Journal of. Research and Development, 2005, 49(2/3): 303-318. DOI: 303

Accellera. Universal verification methodology 1.1 user's guide[M]. Cadence Design System Inc., Mentor Graphics Cor., Synopsys Inc., 2011.

Aharoni M. Solving constraints on the intermediate result of decimal floating-point operations[C]//Proc. 18th IEEE Computer Arithmetic Symp. (ARITH 18). IEEE, 2007: 38-45.

IEEE. IEEE Std 754-2008, IEEE standard for floating-point arithmetic[S]. IEEE, 2008.

冯春阳, 杨靓, 黄士坦. 随机法和Hensel Lifting联合的浮点乘测试用例生成方法[J]. 计算机辅助设计与图形学学报, 2014, 26(9): 1509-1520. DOI: 1509

熊涛, 蒋见花. 基于UVM方法学的纵向可重用研究[J]. 微电子学与计算机, 2016, 33(4): 64-68. DOI: 64

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