An All-Digital Clock and Data Recovery Circuit for Isolated Communication Chip

CHEN Yuan-cong; ZHAO Ye; WANG Tong

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An All-Digital Clock and Data Recovery Circuit for Isolated Communication Chip

更新时间：2026-09-04

- An All-Digital Clock and Data Recovery Circuit for Isolated Communication Chip
- Vol. 33, Issue 12, Pages: 117-120(2016)
- 作者机构：
  
  中国科学院机构微电子研究所,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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陈原聪, 赵野, 王彤. 一种应用于隔离通讯芯片的全数字时钟数据恢复电路[J]. 微电子学与计算机, 2016, 33(12): 117-120.

CHEN Yuan-cong, ZHAO Ye, WANG Tong. An All-Digital Clock and Data Recovery Circuit for Isolated Communication Chip[J]. 2016, 33(12): 117-120.
陈原聪, 赵野, 王彤. 一种应用于隔离通讯芯片的全数字时钟数据恢复电路[J]. 微电子学与计算机, 2016, 33(12): 117-120. DOI：

CHEN Yuan-cong, ZHAO Ye, WANG Tong. An All-Digital Clock and Data Recovery Circuit for Isolated Communication Chip[J]. 2016, 33(12): 117-120. DOI：

摘要

提出一种应用于隔离通讯芯片的全数字时钟数据恢复电路

该时钟数据恢复电路基于单环结构的锁相环进行设计

包括双模式bang-bang鉴频鉴相器

带二进制快速搜索算法和抖动抑制数字滤波器的状态机

以及三级环形数控振荡器等组成部分.电路完全基于0.18 mCMOS工艺库标准单元和硬件描述语言设计

具有锁定速度快、可移植性好、输出抖动小等优点.仿真结果表明该全数字时钟数据恢复电路锁定频率范围为18~80 MHz

能够在10 s内完成频率捕获

输出峰峰抖动137.13 ps

RMS抖动32.39 ps

1.8 V供电电压下整体功耗为1.279 mW@40 MHz.芯片整体版图面积350 mm×250 mm.

Abstract

A kind of all-digital clock and data recovery circuit for isolated communication chip is proposed in this paper. The all-digital clock and data recovery circuit is based on the design of a single phase-locked loop structure. It is composed of dual model bang-bang phase and frequency detect

digital machine with binary search and jitter suppressive digital filter

and ladder-shaped ring digital controlled oscillator with three level control word. The circuit is based on standard cell and hardware description language design

with fast locking

low jitter and good portability. Simulation shows that the locking range of this all-digital clock and data recovery is 18~80 MHz

and it finish the frequency locked in 10 s

the measured peak to peak jitter is about 137.13 ps

RM jitter is 32.39 ps. the circuit consumed the power of 1.279 mW@40 MHz at 1.8 V supply

the layout area is 350 m×250 m.

关键词

Keywords

references

Sheng D, Lan J C. A monotonic and low-power digitally controlled oscillator with portability for SoC applications[C]//Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on. Seoul: IEEE, 2011: 1-4.

Chung C C, Dai W C. A referenceless all-digital fast frequency acquisition full-rate CDR circuit for USB 2.0 in 65nm CMOS technology[C]//VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on. Hsinchu: IEEE, 2011: 1-4.

张刚. CMOS集成锁相环电路设计[M]. 北京: 清华大学出版社, 2013.

Sheng D, Chung C C, LAN J C. A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications[C]//Quality Electronic Design (ASQED), 2012 4th Asia Symposium on. Penang: IEEE, 2012: 123-127.

Hsu H J, Huang S Y. A low-jitter ADPLL via a suppressive digital filter and an interpolation-based locking scheme[J]. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2011, 19(1): 165-170. DOI: 165

尹晶, 曾烈光. 一种快速同步的时钟数据恢复电路的设计实现[J]. 光通信技术, 2007, 31(1): 52-54. DOI: 52

高宁, 张长春, 方玉明, 等. 一种高性能盲过采样时钟数据恢复电路的实现[J]. 微电子学与计算机, 2014, 31(6): 137-140. DOI: 137

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