The Design and Implementation of Data Flow Processing Unit of Dynamical Reconfigurable Array Processor

SHAN Rui; LI Tao; JIANG Lin

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The Design and Implementation of Data Flow Processing Unit of Dynamical Reconfigurable Array Processor

更新时间：2026-09-04

- The Design and Implementation of Data Flow Processing Unit of Dynamical Reconfigurable Array Processor
- Vol. 34, Issue 1, Pages: 106-109(2017)
- 作者机构：
  
  西安邮电大学机构电子工程学院,陕西,西安,710121
- 作者简介：
- 基金信息：
- DOI：
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- Published：2017
- 稿件说明：
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山蕊, 李涛, 蒋林. 动态可重构阵列处理器数据流处理单元的设计与实现[J]. 微电子学与计算机, 2017, 34(1): 106-109.

SHAN Rui, LI Tao, JIANG Lin. The Design and Implementation of Data Flow Processing Unit of Dynamical Reconfigurable Array Processor[J]. 2017, 34(1): 106-109.
山蕊, 李涛, 蒋林. 动态可重构阵列处理器数据流处理单元的设计与实现[J]. 微电子学与计算机, 2017, 34(1): 106-109. DOI：

SHAN Rui, LI Tao, JIANG Lin. The Design and Implementation of Data Flow Processing Unit of Dynamical Reconfigurable Array Processor[J]. 2017, 34(1): 106-109. DOI：

摘要

阵列处理器是一种满足高效能需求、适应未来工艺发展的并行计算结构.基于动态可重构阵列处理器架构

提出了一种基于数据流驱动的处理单元高效硬件实现结构

并完成了四抽头低通滤波器的电路映射及仿真

最后基于Xilinx V6开发板的综合结果进行了性能分析.

Abstract

Array processor is a kind of parallel computing architecture meeting the demand of high performance and adapting the development of technology in the future.This paper proposed a kind of high efficient architecture of processing unit based of data flow driven

completed the mapping and simulation of four tap low-pass filter.Finally

performance analysis was provided according to the synthesize result based on Xilinx v6 development board.

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references

黄虎才. 多态阵列处理器的并行计算研究[D]. 西安: 西安邮电大学, 2014.

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刘禹成. 面向密集数据并行计算的可重构线性阵列处理器架构的设计[D]. 上海: 上海交通大学, 2011.

Curran B W, Jacobi C, Bonanno J J, et al. The IBM z13multithreaded microprocessor[J]. IBM Journal of Research and Development, 2015, 59(4/5): 11-13. DOI: 11

范凯, 谢憬, 毛志刚. 基于动态可重构技术的阵列型处理器设计[J]. 微电子学与计算机, 2010, 27(7): 168-172. DOI: 168

沈绪榜. 阵列处理器系统芯片的发展[J]. 电子产品世界, 2010, 17(1): 10-12. DOI: 10

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