Design and Implementation of Clock Shared a Multithreaded Processor Storage Structure

LI Mao-liang; LI Tao; LIU Huan; YANG Zheng; GUO Jia-le; LI Ming; SONG Chen-yang

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Design and Implementation of Clock Shared a Multithreaded Processor Storage Structure

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- Design and Implementation of Clock Shared a Multithreaded Processor Storage Structure
- Vol. 34, Issue 1, Pages: 110-113(2017)
- 作者机构：
  
  1. 西安邮电大学机构电子工程学院,陕西,西安,710121
  2. 西安邮电大学计算机学院,陕西,西安,710121
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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李卯良, 李涛, 刘欢, 杨铮, 郭佳乐, 李明, 宋晨阳. 时钟共享多线程处理器存储结构的设计与实现[J]. 微电子学与计算机, 2017, 34(1): 110-113,118.

LI Mao-liang, LI Tao, LIU Huan, et al. Design and Implementation of Clock Shared a Multithreaded Processor Storage Structure[J]. 2017, 34(1): 110-113.
李卯良, 李涛, 刘欢, 杨铮, 郭佳乐, 李明, 宋晨阳. 时钟共享多线程处理器存储结构的设计与实现[J]. 微电子学与计算机, 2017, 34(1): 110-113,118. DOI：

LI Mao-liang, LI Tao, LIU Huan, et al. Design and Implementation of Clock Shared a Multithreaded Processor Storage Structure[J]. 2017, 34(1): 110-113. DOI：

摘要

针对时钟共享多线程处理器(SMT_PAAG)中指令和数据存取速率的需求

提出了一种时钟共享多线程处理器交叉存储结构.该结构分为数据交叉存储和指令交叉存储

其中数据交叉存储实现了前向处理单元和多线程处理单元(Processing Element

PE)的数据交互、线程间数据交互以及线程内部数据存取; 指令交叉存储实现了PE内部线程的指令存取.在FPGA上实现结果表明

该交叉存储结构能够满足多线程处理器对于指令和数据存取速率的需求

最高工作频率可达518.309 MHz.

Abstract

For clock shared a multithreaded processor(SMT_PAAG)of instructions and data transfer rate indemand

proposes a shared clock multithreaded processor cross storage structure.The structure is composed of data storage and instruction cross storage.The data storage exchange between the front processing unit and the multi thread processing unit(Element Processing

PE)is realized

data interactions between threads

and thread the internal data access.Instruction cross storage to achieve the PE internal thread instruction access.Implemented on the FPGA results show that the cross-storage structures can meet a multithreaded processor for instructions and data transfer rate of the demand

the highest frequency can reach 518.309 MHz.

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Keywords

references

Li T, Xiao L, Huang H, et al. PAAG: A polymorphic aArray architecture forgraphics and image processing[C]//International Symposium on Parallel Architectures. IEEE, 2012: 242-249.

Spracklen L, Abraham S G. Chip multithreading: opportunities and challenges[C]//International Symposium on High-performance Computer Architecture. Austin, 2005: 248-252.

刘应天. 时钟共享多线程处理单元的设计与实现[D]. 西安: 西安邮电大学, 2015.

Hammond L, Hubbert B A, Siu M, et al. The Stanford Hydra CMP[J]. Micro IEEE, 2000, 20(2): 71-84. DOI: 71

雷晓锋, 李涛. 时钟共享多线程处理器通信机制的设计与实现[J]. 电子技术应用, 2016, 42(3): 42-46. DOI: 42

屈文新, 樊晓桠, 张盛兵. 多核多线程处理器存储技术研究进展[J]. 计算机科学, 2007, 34(4): 13-16. DOI: 13

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