Design of an 11-Bit Pipelined ADC with Improved OPAMP Sharing Configuration

WAN Fu-qiang; DIAO Sheng-xi; LIN Fu-jiang

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Design of an 11-Bit Pipelined ADC with Improved OPAMP Sharing Configuration

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- Design of an 11-Bit Pipelined ADC with Improved OPAMP Sharing Configuration
- Vol. 33, Issue 11, Pages: 119-123(2016)
- 作者机构：
  
  1. 中国科学技术大学微纳电子系统集成研究中心,安徽,合肥,230026
  2. 华东师范大学信息科学与技术学院上海市多维度信息处理重点实验室,上海,200241
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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万富强, 刁盛锡, 林福江. 一种改进运放共享结构的11位流水线ADC设计[J]. 微电子学与计算机, 2016, 33(11): 119-123.

WAN Fu-qiang, DIAO Sheng-xi, LIN Fu-jiang. Design of an 11-Bit Pipelined ADC with Improved OPAMP Sharing Configuration[J]. 2016, 33(11): 119-123.
万富强, 刁盛锡, 林福江. 一种改进运放共享结构的11位流水线ADC设计[J]. 微电子学与计算机, 2016, 33(11): 119-123. DOI：

WAN Fu-qiang, DIAO Sheng-xi, LIN Fu-jiang. Design of an 11-Bit Pipelined ADC with Improved OPAMP Sharing Configuration[J]. 2016, 33(11): 119-123. DOI：

摘要

对流水线模数转换器(ADC)的运放共享结构进行了改进

设计了一款应用于超高频RFID系统的11位100 MS/s采样率的流水线ADC.该ADC将采样保持电路和第一级余量增益电路共享同一个运算放大器

从而提高运算放大器的电流效率

进而减小功耗.运算放大器采用两对差分输入一对差分输出的、带增益自举的直筒式结构.通过使用对称栅压自举开关

减小了连接虚地的开关

流过大电流时

注入电荷的失配.采用此运放共享思路设计的11位流水线ADC

在奈奎斯特采样时

有效位数是10.6 bit

SFDR为71.2 dB

SNDR为65.5 dB

功耗为52 mW.

Abstract

This paper presents the improvement of the OPAMP sharing configuration for the pipelined analog to digital converter (ADC)

and designs an 11-bit and 100 MS/s sampling-rate pipeline ADC for a UHF RFID system. The sample and hold circuit shares the same OPAMP with the first-stage residual gain amplifier circuit

so that current efficiency of OPAMP is improved and power consumption is saved. The OPAMP adopts gain-boost telescope structure with two pairs input and one pair output. By using symmetrical bootstrapped switch

the charge injection mismatch is reduced

when large current flows into virtual ground. The pipeline ADC achieves an ENOB of 10.6 bits

an SFDR of 71.2 dB

an SNDR of 65.5 dB and power consumption of 52 mW at the Nyquist sampling input frequency.

关键词

Keywords

references

Khannur P, Chen X, Yan D, et al. A universal UHF RFID reader IC in 0.18-μm CMOS technology[J]. IEEE J Sol Sta Circ, 2008, 43(5): 114-1155. DOI: 114

Li J, Zeng X, Xie L, et al. A 1.8-V 22-mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling applications[J]. IEEE J Sol Sta Circ, 2008, 43(2): 321-329. DOI: 321

Min B, Kim P, Bowman F, et al. A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC[J]. IEEE J Sol Sta Circ, 2003, 38(12): 2031-2039. DOI: 2031

ParkY-I, Karthikeyan S, TSAY F, et al. A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply[C]//Circuits and Systems, ISCAS, The 2001 IEEE International Symposium on. Sydney: IEEE, 2001: 580-583.

Chiu Y, Gray P, Nikolic B. A 14-b 12-MS/s CMOS Pipeline ADC With Over 100-dB SFDR[J]. IEEE J Sol Sta Circ, 2004, 39(12): 2139-2151. DOI: 2139

周银, 胡靖, 周锋. 一种0.2mm210位50MS/s流水线型模数转换器[J]. 微电子学, 2015, 45(2): 164-168 DOI: 164

丁洋, 王宗民, 周亮, 等. 一种用于16位流水线ADC的多比特子DAC电容失配校准方法[J]. 微电子学与计算机, 2012, 9(6): 172-179. DOI: 172

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