Methods for Measuring Clock Skew on FPGA Devices

XIE Chang-sheng; YU Zong-guang; ZHANG Yan-fei; WANG De-long; HU Kai

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Methods for Measuring Clock Skew on FPGA Devices

更新时间：2026-09-04

- Methods for Measuring Clock Skew on FPGA Devices
- Vol. 34, Issue 6, Pages: 137-140(2017)
- 作者机构：
  
  1. 无锡中微亿芯有限公司,江苏,无锡,214072
  2. 中国电子科技集团公司第五十八研究所,江苏,无锡,214035
- 作者简介：
- 基金信息：
- DOI：
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- Published：2017
- 稿件说明：
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谢长生, 于宗光, 张艳飞, 王德龙, 胡凯. 一种FPGA芯片时钟SKEW的测试方法[J]. 微电子学与计算机, 2017, 34(6): 137-140.

XIE Chang-sheng, YU Zong-guang, ZHANG Yan-fei, et al. Methods for Measuring Clock Skew on FPGA Devices[J]. 2017, 34(6): 137-140.
谢长生, 于宗光, 张艳飞, 王德龙, 胡凯. 一种FPGA芯片时钟SKEW的测试方法[J]. 微电子学与计算机, 2017, 34(6): 137-140. DOI：

XIE Chang-sheng, YU Zong-guang, ZHANG Yan-fei, et al. Methods for Measuring Clock Skew on FPGA Devices[J]. 2017, 34(6): 137-140. DOI：

摘要

随着FPGA规模的扩大和工作频率的提高

时钟Skew成为FPGA越来越重要的性能指标

而如何精确测试芯片中的时钟Skew也就显得尤为重要.对此以JFPGA-YX2芯片为例

介绍一种可以精确测量FPGA时钟Skew的测试方法.将芯片内部的时钟资源通过配置逻辑配置成一系列的环形振荡器

每个振荡器的振荡频率由该振荡器所包含路径的延时决定.对这些振荡器的测量频率值进行运算处理即可获得精确的时钟Skew.

Abstract

During FPGA is becoming larger and clock frequency higher

the clock skew is key factor during design implemented

so its more important to get the clock skew parameter of FPGA clock system when FPGA device design. In the paper

based on JFPGA-YX2 device

introduce methods to measure accurately skew of clock distribution networks on FPGA

it use ring oscillators formed on the device using clock tree and configurable logic

then measure the frequency of the ring oscillator

last calculate and get the clock propagation delay and clock skew.

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references

周宦银, 房宗良, 朱玲赞. 导线中电传输速度的测量[J]. 仪器仪表学报, 2006, 27(增刊1): 95-97. DOI: 95

Chan S. Methods and circuits for measuring clock Skew on programmable logic devices: US, US 6862548 B1[P]. 2005.

伍翠萍, 何波, 于奇, 等. 一种低电压低功耗的环形压控振荡器设计[J]. 微电子学与计算机, 2008, 25(5): 69-72. DOI: 69

周珊, 王金波, 王晓丹. 基于时序路径的FPGA时序分析技术研究[J]. 微电子学与计算机, 2016, 33(1): 76-80. DOI: 76

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