Research on the Converter from IEEE1149.1 to IEEE1149.7

YAN Xue-long; WANG Yang-bing; CHEN Shou-hong

Chinese

您当前的位置：

首页 >

文章列表页 >

Research on the Converter from IEEE1149.1 to IEEE1149.7

更新时间：2026-09-04

- Research on the Converter from IEEE1149.1 to IEEE1149.7
- Vol. 33, Issue 11, Pages: 133-136(2016)
- 作者机构：
  
  1. 桂林电子科技大学机构电子工程与自动化学院,广西,桂林,541004
  2. 广西自动检测技术与仪器重点实验室,广西,桂林,541004
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
移动端阅览
颜学龙, 王洋冰, 陈寿宏. 基于IEEE1149.1至IEEE1149.7转换器的研究与实现[J]. 微电子学与计算机, 2016, 33(11): 133-136, 141.

YAN Xue-long, WANG Yang-bing, CHEN Shou-hong. Research on the Converter from IEEE1149.1 to IEEE1149.7[J]. 2016, 33(11): 133-136.
颜学龙, 王洋冰, 陈寿宏. 基于IEEE1149.1至IEEE1149.7转换器的研究与实现[J]. 微电子学与计算机, 2016, 33(11): 133-136, 141. DOI：

YAN Xue-long, WANG Yang-bing, CHEN Shou-hong. Research on the Converter from IEEE1149.1 to IEEE1149.7[J]. 2016, 33(11): 133-136. DOI：

摘要

IEEE1149.7标准相对于IEEE1149.1标准新增了很多测试与调试的功能

解决了现今复杂度高的芯片和系统无法测试的问题.在深入地研究IEEE1149.1和IEEE1149.7两种标准的基础上

利用自上而下的设计方法完成了由IEEE1149.1信号变为IEEE1149.7信号转换器的设计

在QuartusⅡ平台中通过Verilog语言实现

将设计应用在FPGA中

并用QuartusⅡ中嵌入式逻辑分析仪SignalTapⅡ采集FPGA的输出信号.输出结果表明所设计的方案可以将IEEE1149.1信号转化为IEEE1149.7信号

可用于IEEE1149.7的待测系统进行测试与调试.

Abstract

IEEE1149.7 standard with respect to the IEEE1149.1 standard added a lot of testing and debugging features

to solve the problem of high complexity of todays chips and systems cant be tested. In-depth research foundation IEEE1149.1 and IEEE1149.7 two standards on the use of top-down design method to complete the conversion by the IEEE1149.1 IEEE1149.7 converter design in QuartusⅡ platform by Verilog language the design in FPGA

and SignalTapⅡ embedded logic analyzer capture FPGA output signal in QuartusⅡ. The output results show that the design of the program can transform IEEE1149.1 signal into IEEE1149.7 signal that can be used IEEE1149.7 test system for testing and debugging.

关键词

Keywords

references

徐建洁. 边界扫描测试系统设计与实现[D]. 长沙: 国防科技大学, 2005.

IEEE Std 1149.1-2001. IEEE Standard Test Access Port and Boundary-Scan Architecture[S]. America: IEEE, 2001.

IEEE Std 1149.7. IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture[S]. America: IEEE, 2009.

Francisco R. Gatewaying IEEE 1149.1 and IEEE 1149.7 Test Access Ports[C]//2012 IEEE 18th International On-Line Testing Symposium. Washington DC, USA: ACM, 2012: 136-138.

STPHEN L. Reinventing JTAG for SoC debugging[J]. Electronic Design % Application World-Nikkei Electronics china, 2009, 26(2): 15-19. DOI: 15

徐志磊. 紧凑型JTAG接口的设计与验证[D]. 上海: 上海交通大学, 2010.

黄新, 蔡俊. 基于JTAG的星型扫描技术的研究[J]. 电子技术应用, 2012, 38(3): 88-95. DOI: 88

陈寿宏, 颜学龙, 黄新. 基于IEEE1149.7标准的CJTAG测试设计方法研究[J]. 电子技术应用, 2013, 39(1): 79-82. DOI: 79

杨轲. IEEE 1149.7标准两线星型扫描格式研究[J]. 微电子学与计算机, 2015, 32(10): 147-150. DOI: 147

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Lightweight countermeasures against Spectre attacks on the branch prediction unit

Design of ultra-low power real-time clock circuits

Research on the design of blockchain-based AI-generated content traceability framework

A feature-oriented context understanding and slice analysis network for tuberculosis detection

Research on assembly action recognition based on MSS-YOLO-MPHands fusion architecture

Related Author

No data

Related Institution

No data

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰