A ΔΣ Time-to-Digital Converter Based on Gated-Ring-Oscillator Using Time Amplifier Gain Calibration Technique

XIE Run; DIAO Sheng-xi; LIN Fu-jiang

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A ΔΣ Time-to-Digital Converter Based on Gated-Ring-Oscillator Using Time Amplifier Gain Calibration Technique

更新时间：2026-09-04

- A ΔΣ Time-to-Digital Converter Based on Gated-Ring-Oscillator Using Time Amplifier Gain Calibration Technique
- Vol. 33, Issue 11, Pages: 137-141(2016)
- 作者机构：
  
  中国科学技术大学电子科学与技术系, 微纳电子系统集成电路中心,安徽,合肥,230026
- 作者简介：
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- Published：2016
- 稿件说明：
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谢润, 刁盛锡, 林福江. 一种使用增益校准技术的ΔΣ时间数字转换器[J]. 微电子学与计算机, 2016, 33(11): 137-141.

XIE Run, DIAO Sheng-xi, LIN Fu-jiang. A ΔΣ Time-to-Digital Converter Based on Gated-Ring-Oscillator Using Time Amplifier Gain Calibration Technique[J]. 2016, 33(11): 137-141.
谢润, 刁盛锡, 林福江. 一种使用增益校准技术的ΔΣ时间数字转换器[J]. 微电子学与计算机, 2016, 33(11): 137-141. DOI：

XIE Run, DIAO Sheng-xi, LIN Fu-jiang. A ΔΣ Time-to-Digital Converter Based on Gated-Ring-Oscillator Using Time Amplifier Gain Calibration Technique[J]. 2016, 33(11): 137-141. DOI：

摘要

提出了一种使用门控环形振荡器及级间增益误差校正技术的1-1 MASH结构ΔΣ型TDC.该TDC使用两个GRO-TDC级联

实现二阶噪声整形.采用基于电荷泵的大增益时间放大器进行级间放大

进一步降低了TDC的量化噪声.使用一种级间增益校准技术校正时间放大器增益误差与两级GRO的频率失配.该TDC在SMIC 40 nm 1P8M CMOS工艺下设计和仿真

实现了宽带宽、高精度(低带内积分噪声)、大动态范围.

Abstract

A 1-1 MASH delta-sigma time-to-digital converter using charge-pump based time-amplifier and gain calibration technique is proposed. The TDC using two cascaded gated-ring-oscillator based TDCs and achieved 2nd order noise shaping. By adopting of a high gain charge-pump based time amplifier

the quantization noise of proposed TDC is further diminished. The proposed TDC is designed and simulated on SMIC 40 nm 1P8M CMOS process

achieved high bandwidth

high resolution (low integrated noise) and large dynamic range.

关键词

Keywords

references

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Oh T, Venkatra H, Moom U K. A time-based pipelined adc using both voltage and time domain information[J]. IEEE J Solid-State Circuits, 2014, 49(4): 961-971. DOI: 961

Gande M, Maghari N, OH T, et al. A 71 dB dynamic range third-order TDC using charge-pump[J]. Proc IEEE Symp VLSI Circuits Dig, 2012, 38(7): 168-169. DOI: 168

Yu W, Kim K, Cho S. A integrated noise 4 MHz bandwidth second-order time-to-digital converter with gated switched-ring oscillator[J]. Circuits and Systems I, IEEE Transactions on, 2014, 61(8): 2281-2289. DOI: 2281

Wonskk yu S C, Kwangseok kim. A 0.22 ps rms integrated noise 15 MHz bandwidth fourth-order delta-sigma time-to-digital converter using time-domain error-feedback filter[J]. Solid-State Circuits, IEEE Journal of, 2015, 50(5): 1251-1262. DOI: 1251

Seo Y H, Kim J S, Park H J, et al., A 1.25 ps resolution 8b cyclic TDC in 0.13 m CMOS[J]. Solid-State Circuits, IEEE Journal of, 2012, 41(3): 736-743. DOI: 736

Straayer M Z, Perrott M. A multi-path gated ring oscillator TDC with 1st order noise shaping[J]. Solid State Circuits, IEEE Journal of, 2009, 44(4): 1089-1098. DOI: 1089

Konishi T, Okuno K, Izumi S, et al. A second-order all-digital tdc with low jitter frequency shift oscillators and dynamic flipflops[J]. IEICE transactions on electronics, 2013, 96(4): 546-552. DOI: 546

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