Design of Sub-ADC Applied to 14 Bit Low-Power Pipeline ADC

CHEN Zhong-xue; HE Quan; ZHANG Guo-hao

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Design of Sub-ADC Applied to 14 Bit Low-Power Pipeline ADC

更新时间：2026-09-04

- Design of Sub-ADC Applied to 14 Bit Low-Power Pipeline ADC
- Vol. 34, Issue 1, Pages: 132-135(2017)
- 作者机构：
  
  广东工业大学机构信息工程学院,广东,广州,510006
- 作者简介：
- 基金信息：
- DOI：
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- Published：2017
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陈忠学, 何全, 章国豪. 应用于14bit低功耗流水线ADC的sub-ADC电路设计[J]. 微电子学与计算机, 2017, 34(1): 132-135,140.

CHEN Zhong-xue, HE Quan, ZHANG Guo-hao. Design of Sub-ADC Applied to 14 Bit Low-Power Pipeline ADC[J]. 2017, 34(1): 132-135.
陈忠学, 何全, 章国豪. 应用于14bit低功耗流水线ADC的sub-ADC电路设计[J]. 微电子学与计算机, 2017, 34(1): 132-135,140. DOI：

CHEN Zhong-xue, HE Quan, ZHANG Guo-hao. Design of Sub-ADC Applied to 14 Bit Low-Power Pipeline ADC[J]. 2017, 34(1): 132-135. DOI：

摘要

基于SMIC 0.18m标准CMOS工艺

设计了一种应用于14bit、100 MHz采样频率低功耗流水线ADC的1.5位sub-ADC单元电路.sub-ADC主要包括核心模块比较器电路和编码单元电路.采用由前置放大器和锁存器构成的动态锁存比较器

来实现较高的速率.为降低流水线ADC的每一级功耗

提出一种新结构的sub-ADC电路

实现前置放大器在相邻的比较器中共享

增加复位开关电路降低“回踢”噪声和消除两锁存器之间的相互干扰.仿真结果表明:在3V电源电压、100 MHz的采样频率下

输入输出正确翻转

传输延时为1.73ns

功耗为157.3A

可满足高精度低功耗流水线ADC的性能要求.

Abstract

Design of the 1.5bit sub-ADC applied to 14 bit low-power pipeline ADC circuit.The circuit is fabricated in a 0.18m standard CMOS process provided by SMIC.The sub-ADC mainly includes the core module comparator circuit and the encoder circuit.The high speed is realized by using the dynamic latch comparator which is composed of the preamplifier and the latch.In order to reduce the power consumption of pipelined ADC

a new structure of sub-ADC circuit is proposed

which can realize the sharing of the preamplifier in the adjacent comparator.Increase the reset switch circuit to reduce Kickback noise and eliminate the mutual interference between the two latches.The simulation results show that the input and output correct flip in 100 MHz sampling frequency at 3Vsupply voltage.The transmission delay is 1.73 ns

and the power consumption is 157.28 uA.Can meet the high accuracy and low power pipeline ADC performance requirements.

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references

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周佳宁, 李荣宽. 一种低功耗14位10MS/s流水线A/D转换器[J]. 微电子学与计算机. 2012, 29(4): 49-57. DOI: 49

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