Design of Non-Volatile Synapse Array and Neuron Circuits

YE Yong; KANG Yong; JING Wei-liang; DU Yuan; SONG Zhi-tang; CHEN Bomy

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Design of Non-Volatile Synapse Array and Neuron Circuits

更新时间：2026-09-04

- Design of Non-Volatile Synapse Array and Neuron Circuits
- Vol. 34, Issue 11, Pages: 1-5(2017)
- 作者机构：
  
  1. 中国科学院上海微系统与信息技术研究所, 信息功能材料国家重点实验室机构,上海,200050
  2. 上海新储集成电路有限公司,上海,200122
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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叶勇, 亢勇, 景蔚亮, 杜源, 宋志棠, 陈邦明. 非易失性突触存储阵列及神经元电路的设计[J]. 微电子学与计算机, 2017, 34(11): 1-5.

YE Yong, KANG Yong, JING Wei-liang, et al. Design of Non-Volatile Synapse Array and Neuron Circuits[J]. 2017, 34(11): 1-5.
叶勇, 亢勇, 景蔚亮, 杜源, 宋志棠, 陈邦明. 非易失性突触存储阵列及神经元电路的设计[J]. 微电子学与计算机, 2017, 34(11): 1-5. DOI：

YE Yong, KANG Yong, JING Wei-liang, et al. Design of Non-Volatile Synapse Array and Neuron Circuits[J]. 2017, 34(11): 1-5. DOI：

摘要

传统的神经形态芯片一般采用SRAM阵列来存储突触权重

掉电后数据会丢失

且只能通过单一地址译码进行存取

不利于突触权重的更新.为此

本文基于40 nm先进工艺并结合嵌入式相变存储器设计了一种非易失性突触存储阵列及神经元电路

为神经元的突触权重存储和更新提供了一种有效、高速和低功耗的解决方案.

Abstract

Traditional neuromorphic chips generally use SRAM array to store the synaptic weights

which would lose data once power down. And the SRAM array can only be accessed through a single address decoding

which is not suitable for synaptic weights update. In this paper

a non-volatile synapse array and neuronal circuits based on 40 nm process combining with embedded phase change memory (ePCM) are proposed. This work would provide an effective

high-speed and low-power solution to store and update the neuron synaptic weights.

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references

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Haykin S. Neural networks: a comprehensive foundation[M]. 3rd ed. US, Englewood Cliffs, NJ, Prentice-Hall, Inc., 2007.

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Song Z, Zhan Y P, Cai D, et al. A phase change memory chip based on tisbte alloy in 40 nm standard CMOS technology[J]. Nano-Micro Lett, 2015, 7(2): 172-176. DOI: 172

Indiveri G, Etienne-cummings R, Schemmel J, et al. Neuromorphic silicon neuron circuits[J]. Frontiers in Neuroscience, 2011, 5(5): 1-23. DOI: 1

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