A Second-OrderΔΣ TDC Using Time-Domain Error-Feedback Filter

ZHAO Lei; ZHANG Feng

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A Second-OrderΔΣ TDC Using Time-Domain Error-Feedback Filter

更新时间：2026-09-04

- A Second-OrderΔΣ TDC Using Time-Domain Error-Feedback Filter
- Vol. 35, Issue 2, Pages: 26-31(2018)
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 中国科学院大学机构,北京,100049
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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赵磊, 张锋. 基于时间域误差反馈滤波器的二阶ΔΣ TDC[J]. 微电子学与计算机, 2018, 35(2): 26-31.

ZHAO Lei, ZHANG Feng. A Second-OrderΔΣ TDC Using Time-Domain Error-Feedback Filter[J]. 2018, 35(2): 26-31.
赵磊, 张锋. 基于时间域误差反馈滤波器的二阶ΔΣ TDC[J]. 微电子学与计算机, 2018, 35(2): 26-31. DOI：

ZHAO Lei, ZHANG Feng. A Second-OrderΔΣ TDC Using Time-Domain Error-Feedback Filter[J]. 2018, 35(2): 26-31. DOI：

摘要

在这篇文章中

一个二阶ΔΣ时间数字转换器被提出以获得高的分辨率和宽的信号带宽.所提出的时间数字转换器采用了基于时间域运算电路如时间寄存器、时间加法器等构成的时间域误差反馈滤波器的单环结构.采用SMIC 28 nm工艺设计

Spectre仿真结果表明噪声底约为-84 dBps/Hz

等效到50 Msps没有噪声整形的TDC的分辨率约为1.5 ps

功耗取决于输入时间间隔

在测量间隔1 ns时功耗约为1.24 mW

测量范围可达7.5 ns.

Abstract

In this paper

a second order ΔΣ Time-to-Digital Converter (TDC) is proposed to achieve high resolution and wide signal bandwidth. The proposed TDC is a single-loop architecture based on a time-domain error-feedback filter using time-domain arithmetic circuits such as time registers

time adders and so on. Implemented in SMIC 28 nm CMOS process

spectre simulation results shows the noise floor of the TDC by taking the minimum PSD value of 84 dBps/Hz which corresponds to a 50Msps classical quantizer without noise shaping and with 1.5 ps steps. The TDC power consumption depends on the time difference between input edges

typically about 1.24 mW for 1ns interval measurement

the measurement range can be up to 7.5 ns.

关键词

Keywords

references

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Kim K S, Yu W, Cho S H. A 9 bit, 1.12 ps resolution 2.5 b/stagepipelined time-to-digital converter in 65 nm CMOS using time-register[J]. IEEE J. Solid-State Circuits, 2014, 49(4): 1007-1016. DOI: 1007

Straayer M Z, Perrott M H. A multi-path gated ring oscillatorTDC with first-order noise shaping[J]. IEEE J. Solid-State Circuits, 2008, 44(4): 1089-1098. DOI: 1089

Yu W, Kim K S, Cho S H. A 0.22 psrms integrated noise 15 MHz bandwidth fourth-order ΔΣ time-to-digital converter using time-domain error-feedback filter[J]. IEEE J. Solid-State Circuits, 2015, 50(5): 1251-1262. DOI: 1251

Hong J P, Kim S J, Liu J, et al. A 0.004 mm2 250 uW ΔΣTDC with time-differenceaccumulator and a 0.012 mm2 2.5 mW bang-bang digital PLL usingPRNG for low-power SoC applications[P]. IEEE ISSCC Dig. Tech. Papers, 2012: 240-242.

Elshazly A, Rao S, Young B, et al. A noise-shapingtime-to-digital converter using switched-ringoscillators-Analysis, design, and measurement techniques[J]. IEEE J. Solid-State Circuits, 2014, 49(5): 1184-1197. DOI: 1184

Ng AWL, Zheng S Y, Luong H C. A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2nd-ordernoise-shaping tdc and a transformer-coupled QVCO[J]. ESSCIRC, 2012, 45(3): 189-192. DOI: 189

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