Sliding Window Pipelined High Performance Reconfigurable Viterbi Decoder

ZHAO Xu-ying; LI Huan; WANG Xiao-qin; WANG Dong-lin

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Sliding Window Pipelined High Performance Reconfigurable Viterbi Decoder

更新时间：2026-09-04

- Sliding Window Pipelined High Performance Reconfigurable Viterbi Decoder
- Vol. 35, Issue 2, Pages: 32-36(2018)
- 作者机构：
  
  1. 中国科学院大学机构计算机与控制学院,北京,100190
  2. 中国科学院自动化研究所机构国家专用集成电路设计工程技术研究中心,北京,100190
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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赵旭莹, 李桓, 王晓琴, 王东琳. 基于滑窗流水的高性能可配置viterbi译码器[J]. 微电子学与计算机, 2018, 35(2): 32-36.

ZHAO Xu-ying, LI Huan, WANG Xiao-qin, et al. Sliding Window Pipelined High Performance Reconfigurable Viterbi Decoder[J]. 2018, 35(2): 32-36.
赵旭莹, 李桓, 王晓琴, 王东琳. 基于滑窗流水的高性能可配置viterbi译码器[J]. 微电子学与计算机, 2018, 35(2): 32-36. DOI：

ZHAO Xu-ying, LI Huan, WANG Xiao-qin, et al. Sliding Window Pipelined High Performance Reconfigurable Viterbi Decoder[J]. 2018, 35(2): 32-36. DOI：

摘要

为了对无线通信卷积编码多标准支持

同时为了适应未来高速率卷积编码需求

基于滑窗流水的前向回溯基四算法

实现了支持多标准的高性能可配置viterbi译码器

该译码器峰值吞吐可达到1.15Gbps@6144bit

600 MHz.与主流商用viterbi译码器相比

全球领先的半导体公司-TI的viterbi译码器VCP2数据处理能力为9.5 Mbps@40bit

333 MHz

本文中译码器数据处理能力为32.173 Mbps@40bit

333 MHz

性能提升约3.3倍.此外

该译码器在面积与功耗方面也优于其它可配置型viterbi译码器

在未来高速率卷积译码中有很大应用前景.

Abstract

In order to support multi-standard for convolutional coding in wireless communication

and to meet the requirement of high data rate in the future. A radix-4 multi-standard high performance reconfigurable viterbi decoder based on the sliding window pipeline technique with forward traceback algorithm was implemented. The peak throughput of the decoder can reach up to 1.15Gbps@6144bit

600MHz. Compared with the mainstream commercial viterbi decoder

the data processing speed of VCP2 which is proposed by Texas Instruments company is 9.5Mbps@40bit

333MHz

and the data processing speed of viterbi decoder in this paper is 32.173Mbps@40bit

333MHz

performance improved about 3.3 times. In addition

the decoder is superior to other reconfigurable viterbi decoders in area and power consumption. It has great application prospect in the future high data rate convolutional decoding.

关键词

Keywords

references

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Liu X, Papaefthymiou M C. Design of a high-throughput low-power IS95 viterbi decoder[C]//Design Automation Conference. New Orleans, USA, 2002 : 263-268.

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Muhammad B A, Zanna M A, Mohammed D A, et al. Low complexity FPGA implementation of register exchange based viterbi decoder[C]// IEEE International Conference on Emerging % Sustainable Technologies for Power % ICT in A Developing Society. Islamabad, Pakistan, IEEE, 2013: 21-25.

Gang Y, Erdogan A T, Arslan T. An efficient pre-traceback architecture for the viterbi decoder targeting wireless communication applications[J]. Circuits % Systems Ⅰ Regular Papers IEEE Transactions on, 2006, 53(9): 1918-1927. DOI: 1918

Manzoor R, Rafique A, Bajwa K B. VLSI implementation of an efficient pre-trace back approach for viterbi algorithm[C]//International Bhurban Conference on Applied Sciences % Technology. English, 2007: 27-30.

He J, Liu H, Wang Z, et al. High-speed low-power viterbi decoder design for TCM decoders[J]. IEEE Transactions on Very Large Scale Integration Systems, 2012, 20(20): 755-759. DOI: 755

Anders M A, Mathew S K, Hsu S K, et al. A 1.9 Gb/s 358 mW 16-256 state reconfigurable viterbi accelerator in 90 nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2008, 43(1): 214-222. DOI: 214

夏飞, 聂晶, 李荣春, 等. 现场可编程门阵列参数化多标准高吞吐率基4 Viterbi译码器[J]. 国防科技大学学报, 2016, 38(1): 86-92. DOI: 86

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