Design and Implementation of Micro Architecture for Reconfigurable Computing System

CHAI Zhen; CHAI Zhi-lei; WU Dong

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Design and Implementation of Micro Architecture for Reconfigurable Computing System

更新时间：2026-09-04

- Design and Implementation of Micro Architecture for Reconfigurable Computing System
- Vol. 34, Issue 8, Pages: 33-37(2017)
- 作者机构：
  
  1. 江南大学物联网工程学院,江苏,无锡,214122
  2. 数字工程与先进计算国家重点实验室,江苏,无锡,214125
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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柴镇, 柴志雷, 吴东. 一种可重构计算系统的微架构设计与实现[J]. 微电子学与计算机, 2017, 34(8): 33-37.

CHAI Zhen, CHAI Zhi-lei, WU Dong. Design and Implementation of Micro Architecture for Reconfigurable Computing System[J]. 2017, 34(8): 33-37.
柴镇, 柴志雷, 吴东. 一种可重构计算系统的微架构设计与实现[J]. 微电子学与计算机, 2017, 34(8): 33-37. DOI：

CHAI Zhen, CHAI Zhi-lei, WU Dong. Design and Implementation of Micro Architecture for Reconfigurable Computing System[J]. 2017, 34(8): 33-37. DOI：

摘要

为了推动FPGA计算的大规模应用，设计并实现了一种基于动态部分可重构机制的FPGA计算系统微架构.该架构提供了一套提升FPGA开发效率的用户开发模式，可在FPGA中支持SIMD/MIMD并行计算模式，并通过可重构计算单元的通信支持流水计算模式.实验结果表明，该架构在保持FPGA计算系统高性能、低功耗优势的同时，可有效地简化用户的编程模式.

Abstract

In order to promote the large-scale application of FPGA computation

a micro architecture of FPGA based on dynamic partial reconfiguration mechanism is designed and implemented. The architecture provides a set of user-development mode that can improve the development efficiency of FPGA

which can support SIMD/MIMD parallel computing mode in FPGA

and supports pipeline mode through communication of reconfigurable units. The experimental results show that the architecture can effectively simplify the users programming mode while maintaining the high performance and low power consumption of FPGA computing system.

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references

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