WANG Ming-zhe, XUE Chang-bin, ZHANG Xue-quan. FPGA Design and Implementation of Real-time 2D-DWT in Space Image Compression System[J]. 2017, 34(7): 33-36.
WANG Ming-zhe, XUE Chang-bin, ZHANG Xue-quan. FPGA Design and Implementation of Real-time 2D-DWT in Space Image Compression System[J]. 2017, 34(7): 33-36.DOI:
FPGA Design and Implementation of Real-time 2D-DWT in Space Image Compression System
The standard recommended by CCSDS for space image compression includes a three-level two-dimensional discrete wavelet transform
which is suitable for design and implementation on logical circuit. In this article
a VLSI architecture of 5/3 2D-DWT is proposed
which can meet the demand of real-time processing. This structure adopts pipelined designing and uses the localization of wavelet to compute row and column transform in the same time. As for three-level discrete wavelet transform
this structure adopts pipelined designing either. This structure can reduce the memory usage and the delay of read and write
increase the speed of wavelet transform
make full use of logical resources of FPGA
and reduce the demand of external RAM. Experiment results show that this structure can meet the demand of real-time processing entirely
and provided favorable conditions for coding and transmission.
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references
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