The Design of Ultra-Low Power Wake-Up Receivers Applied to ETCS

LIU Guo-zheng; HUANG Shui-long

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The Design of Ultra-Low Power Wake-Up Receivers Applied to ETCS

更新时间：2026-09-04

- The Design of Ultra-Low Power Wake-Up Receivers Applied to ETCS
- Vol. 35, Issue 2, Pages: 43-48(2018)
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 中国科学院大学机构,北京,101408
  3. 新一代通信射频芯片技术北京市重点实验室,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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刘国政, 黄水龙. 应用于ETCS超低功耗唤醒接收机的设计[J]. 微电子学与计算机, 2018, 35(2): 43-48.

LIU Guo-zheng, HUANG Shui-long. The Design of Ultra-Low Power Wake-Up Receivers Applied to ETCS[J]. 2018, 35(2): 43-48.
刘国政, 黄水龙. 应用于ETCS超低功耗唤醒接收机的设计[J]. 微电子学与计算机, 2018, 35(2): 43-48. DOI：

LIU Guo-zheng, HUANG Shui-long. The Design of Ultra-Low Power Wake-Up Receivers Applied to ETCS[J]. 2018, 35(2): 43-48. DOI：

摘要

基于DSRC标准

介绍了唤醒接收机在ETCS中的应用

通过采用提出的设计方案

设计一款低功耗

高灵敏度唤醒接收机.基于0.13 m CMOS工艺

实现了偏置电路

放大电路

比较器

电流基准源和驱动等电路模块.采用优化的电路结构

使得运放有较低功耗和高增益.为了减小噪声和比较器自身失调对比较器输出的影响

采用带迟滞功能的比较器.仿真结果表明

唤醒接收机可工作在2~3.3V电源电压

-40~80度下

典型情况下基带的检测灵敏度为-68.3 dBm

直流电流为6.97 A.

Abstract

Based on the standard of DSRC

paper introduce the application of wake-up receivers in ETCS. By using the proposed design scheme

wake-up receiver has been achieved

which have low power and high sensitivity. The circuit module

such as bias circuit

amplifier circuit

comparator

current reference source and drive

are implemented based on 0.13 m CMOS process. The op amp has lower power consumption and high gain by using optimizing structure of circuit. A comparator with hysteresis is used to reduce the interference of noise and comparator offset on the comparator output. Simulation result shows that the wake-up receiver can work in the 2 V~3.3 V power supply voltage and -40~80℃ temperature. The detection sensitivity of the baseband is -68.3 dBm and the DC current is 6.97 A typically.

关键词

Keywords

references

Zhu Wenrui, Yang Haigang, Gao Tongqiang, et al. A baseband circuit for wake-up receivers with double-modedetection and enhanced sensitivity robustness[J]. Journal of Semiconductors, 2013, 34(8): 144-149. DOI: 144

周仁杰, 莫太山, 甘业兵, 等. 用于5.8 GHz ETC超低功耗唤醒接收机模拟前端[J]. 半导体技术, 2013, 38(7): 487-491. DOI: 487

Zou J, Zhu S, Feng K, et al. Design of low power wake-up circuits applied to obu system chip[C]// Int. Microw. Millimeter Wave Technol. Conf. China, Shenzhen, 2012: 1-4.

Willy M C Sansen. Analog design essentials[M]. 北京: 清华大学出版社, 2007.

ZhangW, Wang Z, ZhangC. A 6.93 μW wake-up circuit for active RFID tags[C]//Asia Pacific Conference on Postgraduate Research in Microelectronics % Electronics. China, Shanghai, 2009: 452-455.

HuangX, Rampu S, Wang X, et al. A 2.4GHz/915 MHz 51 μW wake-up receiver with offset and noise suppression[C]//IEEE International Solid-State Circuits Conference. USA, San Francisical, 2010: 222-223.

Allen P E, Holberg D R. CMOS模拟集成电路设计[M]. 二版. 冯军, 李智群, 译. 北京: 电子工业出版社, 2011.

Choi J, Lee I Y, Lee K, et al. A 5.8 GHz DSRC transceiver with a 10 μA interference-aware wake-up receiver for the chinese ETCS[J]. IEEE Transactions On Microwave Theory And Techniques, 2014, 62(12): 3146-3160. DOI: 3146

New York Razavi B. Design of analog CMOS integrated circuits[M]. New York: McGraw Hill, 2002.

Choi J, Lee K, Yun S O, et al. An interference-aware 5.8GHz wake-up radio for ETCS[C]// IEEE International Solid-State Circuits Conference. San Francisco, California, 2012: 446-448.

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