Design of Adders for RRAM-based In-memory Computing Using Majority-Inverter Graphs

LIU Wen-kai; FAN Dong-yu; DAI Lan; ZHANG Feng

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Design of Adders for RRAM-based In-memory Computing Using Majority-Inverter Graphs

更新时间：2026-09-04

- Design of Adders for RRAM-based In-memory Computing Using Majority-Inverter Graphs
- Vol. 34, Issue 12, Pages: 50-54(2017)
- 作者机构：
  
  1. 北方工业大学机构电子信息与工程学院,北京,100144
  2. 中国科学院机构微电子研究所微电子重点研究室,北京,100029
- 作者简介：
- 基金信息：
- DOI：
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- Published：2017
- 稿件说明：
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刘文楷, 范冬宇, 戴澜, 张锋. 基于RRAM的运用MIG逻辑设计的加法器电路[J]. 微电子学与计算机, 2017, 34(12): 50-54.

LIU Wen-kai, FAN Dong-yu, DAI Lan, et al. Design of Adders for RRAM-based In-memory Computing Using Majority-Inverter Graphs[J]. 2017, 34(12): 50-54.
刘文楷, 范冬宇, 戴澜, 张锋. 基于RRAM的运用MIG逻辑设计的加法器电路[J]. 微电子学与计算机, 2017, 34(12): 50-54. DOI：

LIU Wen-kai, FAN Dong-yu, DAI Lan, et al. Design of Adders for RRAM-based In-memory Computing Using Majority-Inverter Graphs[J]. 2017, 34(12): 50-54. DOI：

摘要

本文采用SMIC 0.18 m CMOS工艺

设计了一种基于阻变随机存储器(RRAM)的加法器电路.区别于传统的蕴含逻辑(IMP)型加法器

本设计选取新型的多数表决器逻辑(Majority-Inverter Graph

MIG)实现加法运算.文中设计并验证了基于MIG逻辑的一位全加器的全部运算

证明了新逻辑在存储器计算方面的可行性.与传统RRAM一位全加器相比较

本设计的一位全加器因为采用新的逻辑方法使得RRAM多个单元可以并行进行数据操作

从而减少了运算步骤

及原有冗长运算引起的误差

有效提高了运算速度

为存储器内部计算提供了新的思路.

Abstract

Implemented with 0.18 m CMOS process

an adder circuit based on RRAM was presented. Different from the traditional RRAM adder based on implication operation

in the paper

we propose an emerging approach for the synthesis of RRAM-based adders using novel Majority-Inverter Graphs (MIGs). Experimental results show a full adder using MIG can achieve the whole function. Compared with the full adder based on implication

it reduces the number of computing steps obviously by parallel operation among several RRAM cells which lowers the error and improves the computing speed at the same time. This design also provides a new way of in-memory computing.

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Keywords

references

Amaru L, Gaillardon P E, De Micheli G. Majority-inverter graph: a novel data-structure and algorithms for efficient logic optimization[C]// Design Automation Conference. San Francisco, ACM, 2014: 1-6.

Shirinzadeh S, Soeken M, Gaillardon P E, et al. Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs[C]// Design, Automation % Test in Europe Conference % Exhibition. Nice, France, IEEE, 2016: 948-953.

Esch J. Prolog to circuit elements with memory: memristors, memcapacitors, and meminductors[J]. the IEEE, 2009, 97(10): 1715-1716. DOI: 1715

Yang Y, Mathew J, Pontarelli S, et al. Complementary resistive switch-based arithmetic logic implementations using material implication[J]. IEEE Transactions on Nanotechnology, 2016, 15(1): 94-108. DOI: 94

Borghetti J, Snider G S, Kuekes P J, et al. 'Memristive' switches enable 'stateful' logic operations via material implication. [J]. Nature, 2010, 464(7290): 873. DOI: 873

Chua L O, Kang S M. Memristive devices and systems[J]. the IEEE, 1976, 64(2): 209-223. DOI: 209

宋焕章, 王保恒, 张春元. 计算机原理与设计(下册)——存储与外设[M]. 长沙: 国防科技大学出版社, 1999.

张娜. 基于忆阻器的加法器和乘法器高效设计与模拟[D]. 长沙: 国防科学技术大学, 2011.

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