Design of JESD204B Transmitter Interface Using Parallel 8b/10b Encoder

LI Chang-qing; CHENG Jun; LI Liang; GONG Liao

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Design of JESD204B Transmitter Interface Using Parallel 8b/10b Encoder

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- Design of JESD204B Transmitter Interface Using Parallel 8b/10b Encoder
- Vol. 34, Issue 8, Pages: 70-75(2017)
- 作者机构：
  
  1. 西安交通大学微电子学院,陕西,西安,710049
  2. 中国电科集团第24研究所模拟集成电路重点实验室,重庆,400060
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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李长庆, 程军, 李梁, 龚燎. 采用并行8b/10b编码的JESD204B接口发送端电路设计[J]. 微电子学与计算机, 2017, 34(8): 70-75.

LI Chang-qing, CHENG Jun, LI Liang, et al. Design of JESD204B Transmitter Interface Using Parallel 8b/10b Encoder[J]. 2017, 34(8): 70-75.
李长庆, 程军, 李梁, 龚燎. 采用并行8b/10b编码的JESD204B接口发送端电路设计[J]. 微电子学与计算机, 2017, 34(8): 70-75. DOI：

LI Chang-qing, CHENG Jun, LI Liang, et al. Design of JESD204B Transmitter Interface Using Parallel 8b/10b Encoder[J]. 2017, 34(8): 70-75. DOI：

摘要

为解决高速数据采样器采样数据的准确传输问题，对高速串行数据传输协议JESD204B进行了研究和设计.采用了一种名为并行编码的8b/10b编码电路，以减轻系统时钟的负担，提高数据传输速率，完成了发生器接口电路的设计.文中使用Altera公司的Arria V GT FPGA开发板和QUARTUS Ⅱ的静态时序分析工具对所设计的接口电路和并行编码结构进行了验证和分析.结果表明设计的接口电路功能正确，性能满足高速数据传输的要求；并行8b/10b编码电路可以显著提高数据传输率，降低系统时钟的要求.

Abstract

The high-speed serial data transmission protocol JESD204B is studied and designed in order to solve the accurate transmission of high-speed AD sampling data. In the design of the interface circuit

a 8b/10b coding structure called parallel coding is adopted to reduce the burden of the system clock and improve the data transmission rate

the design of the transmitter interface circuit is completed.In this paper

we use the Arria V GT FPGA development board and QUARTUS Ⅱ static timing analysis tool to verify and analyze the structure of the design of the interface circuit and the parallel code.The experimental results show that the design of the interface circuit is correct and the performance meets the requirements of high speed data transmission. The 8b/10b coding structure can significantly improve the data transmission rate and reduce system clock requirements.

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references

JEDEC. JESD204[S]. JEDECSolid State Technology Association, 2011.

JEDEC. JESD204[S]. JEDECSolid State Technology Association, 2006.

Jan M Rabaey, Anantha Chandrakasan, Borivoje Nikolic. 数字集成电路-电路、系统与设计(第2版)[M]. 北京, 电子工业出版社, 2009.

霍兴华, 姚亚峰, 贾茜茜, 等. JESD204B接口协议中的加扰电路设计[J]. 电视技术, 2014, 38(23): 64-67. DOI: 64

杨佩, 张丽娜, 张洵颖, 等. LVDS中8B/10B编码解码器的设计与实现[J]. 微电子学与计算机, 2014, 31(5): 41-48. DOI: 41

周典淼, 徐晖, 陈维华, 等. 基于JESD204B协议的数据传输接口设计[J]. 电子科技, 2015, 28(10): 53-60. DOI: 53

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