Research on MLC NAND Flash Memory Based on Weighted Bit-flipping Decoding Algorithm

ZHANG Xuan; YU Juan

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Research on MLC NAND Flash Memory Based on Weighted Bit-flipping Decoding Algorithm

更新时间：2026-09-04

- Research on MLC NAND Flash Memory Based on Weighted Bit-flipping Decoding Algorithm
- Vol. 35, Issue 2, Pages: 75-78(2018)
- 作者机构：
  
  1. 西安理工大学机构,陕西,西安,710082
  2. 陕西师范大学,陕西,西安,710062
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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张旋, 余娟. 基于加权比特翻转的MLC型NAND闪存系统[J]. 微电子学与计算机, 2018, 35(2): 75-78.

ZHANG Xuan, YU Juan. Research on MLC NAND Flash Memory Based on Weighted Bit-flipping Decoding Algorithm[J]. 2018, 35(2): 75-78.
张旋, 余娟. 基于加权比特翻转的MLC型NAND闪存系统[J]. 微电子学与计算机, 2018, 35(2): 75-78. DOI：

ZHANG Xuan, YU Juan. Research on MLC NAND Flash Memory Based on Weighted Bit-flipping Decoding Algorithm[J]. 2018, 35(2): 75-78. DOI：

摘要

多级单元(Multi-Level-Cell

MLC)技术增加了NAND闪存的存储密度

但也增强了单元间干扰(Cell-to-Cell Interference

CCI)噪声强度

导致了NAND闪存的可靠性急剧下降.在深入研究MLC闪存模型和CCI噪声模型基础上

提出了一种MLC型NAND闪存的加权比特翻转硬判决译码方法.仿真结果表明

在MLC闪存信道条件下

该方法既可保证MLC闪存单元的可靠性

对可保持较低的译码复杂度

从而实现了译码复杂度和性能间的良好折衷.

Abstract

Multi-level cell(MLC) increases the storage density of NAND flash memory

while the Cell-to-Cell interference (CCI) is enhanced

and the reliability of NAND flash memory is decreased. On the research of MLC channel model and CCI noise model

this paper proposes a weighted bit-flipping decoding algorithm for MLC NAND flash memory. The simulation results show that this method can ensure the reliability of the NAND flash memory

while maintaining low decoding complexity

so as to realize a better tradeoff between complexity and decoding performance.

关键词

Keywords

references

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CHAUDHRY A, GUANG Y, CAI K. Read and write voltage signal optimization for multi-level-cell (MLC) NAND flash memory[J]. IEEE Transactions on Com- munications, 2016, 64(4): 1613-1623. DOI: 1613

SUH K, SUH B, LIM Y, et al. A 3.3V 32Mb NAND flash memory with incremental step pulseprogramming scheme[J]. IEEE Journal of Solid-State Circuits, 1995, 30(11): 1149-1156. DOI: 1149

SALA F, IMMINK K, DOLECEK L. Error control schemes for modern flash memories solutions for flash deficiencies[J]. IEEE Consumer Electronics Magazine, 2015, 4(1): 66-73. DOI: 66

TOFAR C, YU T. Dynamic weighted bit-flipping decoding algorithms for LDPC codes[J]. IEEE Transactions on Communi- cations, 2015, 63(11): 3950-3963. DOI: 3950

PARK K, KANG M, KIM D, et al. A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories[J]. IEEE Journal of Solid-State Circuits, 2008, 43(4): 919-928. DOI: 919

张高远, 周亮, 文红. LDPC码加权比特翻转译码算法研究[J]. 电子与信息学报, 2014, 36(9): 2093-2097. DOI: 2093

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