Research on Single-Event Transients Sensitivity in Phase-Locked Loops Based on PDSOI Process

YU Meng; ZENG Chuan-bin; YAN Wei-wei; LI Bo; GAO Lin-chun; LUO Jia-jun; HAN Zheng-sheng

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Research on Single-Event Transients Sensitivity in Phase-Locked Loops Based on PDSOI Process

更新时间：2026-09-04

- Research on Single-Event Transients Sensitivity in Phase-Locked Loops Based on PDSOI Process
- Vol. 34, Issue 8, Pages: 76-81(2017)
- 作者机构：
  
  1. 中国科学院大学机构,北京,101408
  2. 中国科学院微电子研究所,北京,100029
  3. 中国科学院机构硅器件技术重点实验室,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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于猛, 曾传滨, 闫薇薇, 李博, 高林春, 罗家俊, 韩郑生. 基于PDSOI的锁相环电路单粒子瞬变敏感性研究[J]. 微电子学与计算机, 2017, 34(8): 76-81.

YU Meng, ZENG Chuan-bin, YAN Wei-wei, et al. Research on Single-Event Transients Sensitivity in Phase-Locked Loops Based on PDSOI Process[J]. 2017, 34(8): 76-81.
于猛, 曾传滨, 闫薇薇, 李博, 高林春, 罗家俊, 韩郑生. 基于PDSOI的锁相环电路单粒子瞬变敏感性研究[J]. 微电子学与计算机, 2017, 34(8): 76-81. DOI：

YU Meng, ZENG Chuan-bin, YAN Wei-wei, et al. Research on Single-Event Transients Sensitivity in Phase-Locked Loops Based on PDSOI Process[J]. 2017, 34(8): 76-81. DOI：

摘要

分析了一款基于0.35 μm PDSOI工艺的锁相环（PLL）电路的抗单粒子瞬变（SET）能力，利用相位抖动为表征参数评估SET对PLL电路的影响与产生影响的可能性.电路级仿真采用优化过的SET注入模型，提高了仿真预测的准确程度.分析了PLL电路的SET敏感节点与敏感工作状态，仿真与激光测试表明，分频器（DIV）与输出低压正发射极耦合逻辑（LVPECL）是最敏感的电路模块，其内部节点的敏感性与节点分布和电路工作状态关系密切.最恶劣情况下相位抖动可达输出周期的一半左右，分析结果有助于抗SET加固设计.

Abstract

Single-event transients (SET) sensitivity of a Phase-Locked-Loops (PLL) based on 0.35 μm PDSOI process has been analyzed. By measuring the phase jitter of PLLs output

the impacts of SET and their occurring possibility have been evaluated. An optimized SET injection model was used in circuit level simulation to improve the accuracy of simulation prediction. The SET sensitive nodes and operating condition of circuit are analyzed

and the results show that frequency divider (DIV) and output Low Voltage Positive Emitter-Couple Logic (LVPECL) are the most sensitive sub-circuits

whose SET sensitivities are close related to their working condition. In the worst case

phase jitter can be up to about half of the output cycle. Analysis results would be helpful to the design of radiation hardening.

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references

Chung H H, Chen W, Bakkaloglu B, et al. Analysis of single events effects on monolithic PLL frequency synthesizers[J]. IEEE Transactions on Nuclear Science, 2006, 53: 3539-3543. DOI: 3539

Bi J S, Zeng C B, Gao L C, et al. Effects of metal spacing and poly-silicon layers on pulsedlaser single eventtransient testing[C]// 2014 IEEE International Conference on Microelectronic Test Structures. IEEE, 2014: 207-212.

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Bi JinShun, Zeng ChuanBin, Gao LinChun, et al. "Estimation of pulsed laser-induced single event transient in a partially depleted silicon-on-insulator 0.18-μm MOSFET"[J]. Chinese Physics B, 2014, 23: 631-635. DOI: 631

Boulghassoul Y, Massengill L W, Sternberg A L, et al. Towards SET mitigation in RF digital PLLs: From error characterization to radiation hardening considerations[J]. IEEE Transactions on Nuclear Science, 2006, 53: 2047-2053. DOI: 2047

Zhao Z, Zhang M, Chen J, et al. A single-event transient hardened phase-locked loop in 0.18 mu m CMOS process[C]// IEEE International Conference on Asic. IEEE, 2009: 284-287.

Loveless T D, Massengill L W, Bhuva B L, et al. A probabilistic analysis technique applied to a radiation-hardened-by-design voltage-controlled oscillator for mixed-signal phase-locked loops[J]. IEEE Transactions on Nuclear Science, 2008, 55: 3447-3455. DOI: 3447

Kauppila J S, Sternberg A L, Alles M L, et al. A bias-dependent single-event compact model implemented into BSIM4 and a 90 nm CMOS process design kit[J]. IEEE Transactions on Nuclear Science, 2009, 56: 3152-3157. DOI: 3152

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