The Methodology and Implementation for Recognition of Complex Topology During Timing Model Extraction

DUAN Fen; JIN Xiang-liang

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The Methodology and Implementation for Recognition of Complex Topology During Timing Model Extraction

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- The Methodology and Implementation for Recognition of Complex Topology During Timing Model Extraction
- Vol. 35, Issue 1, Pages: 86-90(2018)
- 作者机构：
  
  1. 湘潭大学机构物理与光电工程学院,湖南,湘潭,411105
  2. 湖南省微光电与系统集成工程实验室,湖南,湘潭,411105
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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段芬, 金湘亮. 时序模型提取中复杂单元拓扑结构识别的实现研究[J]. 微电子学与计算机, 2018, 35(1): 86-90, 95.

DUAN Fen, JIN Xiang-liang. The Methodology and Implementation for Recognition of Complex Topology During Timing Model Extraction[J]. 2018, 35(1): 86-90.
段芬, 金湘亮. 时序模型提取中复杂单元拓扑结构识别的实现研究[J]. 微电子学与计算机, 2018, 35(1): 86-90, 95. DOI：

DUAN Fen, JIN Xiang-liang. The Methodology and Implementation for Recognition of Complex Topology During Timing Model Extraction[J]. 2018, 35(1): 86-90. DOI：

摘要

基于NanoTime对不同复杂D触发器和多米诺机构采取不同的处理方式

解决了单元拓扑结果识别错误的问题.结合一个单元的实际案例进行仿真验证

结果显示基于所述的处理方式可以提取出有效的单元时序模型.目前相应的设计已投入流片

成功应用于实际工程应用中

这也说明其具有可靠的实际应用价值

对工程应用设计具有重要意义.

Abstract

In the process of chip design

timing model extraction is one of the key of static timing analysis. Different complex D flip-flop and domino structure need different approaches based on the NanoTime to solve complex topology recognition error

which improves the effectiveness of timing model. The simulation results are shown using an actual case. The simulation data shows that effective timing model can be achieved according to the method provided by this paper. At the present

the corresponding design flow has been invested and successfully applied in practical engineering implementation. This also means it has practical applications value of reliability and it is necessary for engineering implementation.

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references

Jouppi N P. Timing analysis and performance improvement of MOS VLSI designs[J]. IEEE Trans, Computer-Aided Design Integrated Circuits and System, 1987, 6(4), 650-665. DOI: 650

BlaauwD, Chopra K, Srivastava A, et al. Statistical timing analysis: from basic principles to state of the art[J]. IEEE Trans, Computer- Aided Design Integrated Circuits and System, 2008, 27(4): 589-607. DOI: 589

刘峰. 集成电路静态时序分析与建模[M]. 北京: 机械工业出版社, 2016.

孟祥志, 杨萌, 来金梅. 基于累积频数统计的FPGA互连资源时序库[J]. 计算机工程, 2013, 39(2): 254-259. DOI: 254

陈超文. 面向光纤通道的SerDes电路IP化技术研究[D]. 成都: 电子科学大学, 2014.

王东, 陈岚, 冯燕. 一种基于40nm CMOS工艺的电流舵DAC IP[J]. 微电子学与计算机, 2017, 34(2): 25-29. DOI: 25

王东, 陈岚, 柳臻朝, 等. 基于40nm CMOS工艺的DAC IP核物理与时序建模[J]. 微电子学与计算机, 2015, 32(2): 56-59. DOI: 56

袁甲, 张苏敏, 商新超, 等. 一种基于商用标准单元库的极低电压电路设计方法[J]. 微电子学与计算机, 2014, 31(12): 56-59. DOI: 56

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