Design and Implementation of Control Element of RV32I

ZHANG Xun-zhen; LIANG Qing; LI Tao

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Design and Implementation of Control Element of RV32I

更新时间：2026-09-04

- Design and Implementation of Control Element of RV32I
- Vol. 35, Issue 3, Pages: 74-78(2018)
- 作者机构：
  
  西安邮电大学机构电子工程学院,陕西,西安,710121
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
移动端阅览
张迅珍, 梁青, 李涛. RV32I控制单元设计与实现[J]. 微电子学与计算机, 2018, 35(3): 74-78, 82.

ZHANG Xun-zhen, LIANG Qing, LI Tao. Design and Implementation of Control Element of RV32I[J]. 2018, 35(3): 74-78.
张迅珍, 梁青, 李涛. RV32I控制单元设计与实现[J]. 微电子学与计算机, 2018, 35(3): 74-78, 82. DOI：

ZHANG Xun-zhen, LIANG Qing, LI Tao. Design and Implementation of Control Element of RV32I[J]. 2018, 35(3): 74-78. DOI：

摘要

针对新型开源精简指令集架构RISC-V指令集

设计了一款支持32位基本指令集的处理器(RV32I)

其外围电路包含快速存储(QMEM)、高速缓存(Cache)和双倍速率同步动态随机存储器(DDR)等存储设备

主要描述其控制单元的设计与实现.设计采用经典三级流水线

即取指、译码和执行

通过有限状态机支持流水线

并且使用可综合的Verilog HDL语言描述

预留中断异常控制模块.仿真结果表明

该控制单元能够实现流水线正常稳定的运转.

Abstract

RV32I

a processor that supports 32-bit basic instruction sets

is designed to support the new open Reduced Instruction Set Computer RISC-V instruction set. The memory devices of its peripheral circuits include Quick Memory

Cache Memory and Synchronous Dynamic Random Access Memory. This paper focuses on the design and implementation of the control element of RV32I. It uses the classic three-stage pipeline-via finite-state machine to support-fetch

decode and execute and uses the synthesizable Verilog HDL language to describe. And reserved the control element of interrupt and exception. Simulation results show that the control element can realize the the pipeline operation normal and stable.

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references

Andrew Waterman, Lee Yunsup, David A Patterson, et al. The RISC-V instruction set manual, Volume I: User-level ISA version 2.1[R]. Berkeley: University of California, 2016.

Muralidaran. Vijayaraghavan. A memory model for RISC-V[C]//5th RISC-V Workshop Proceedings. IDT, 2016.

Rick O'Connor. Intro % foundation overview[C]//4th RISC-V Workshop Proceedings. IDT, 2016.

Andrew Waterman, Lee Yunsup, Rimas Avizienis, et al. The RISC-V instruction set manual, Volume Ⅱ: Rrivileged architecture version 1.9[R]. Berkeley: University of California, 2016.

Caroline Trippel. A memory consistency model for RISC-V[C]//5th RISC-V Workshop Proceedings. IDT, 2016.

雷思磊. 步步惊"芯": 软核处理器内部设计分析[M]. 北京: 电子工业出版社, 2013.

Krste Asanovic, Interrupts[C]//4th RISC-V Workshop Proceedings. IDT, 2016.

雷思磊. RISC-V架构的开源处理器及SoC研究综述[J]. 单片机与嵌入式系统应用, 2017, 17 (2) : 56-60. DOI: 56

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