Design and Implementation of Embedded GPU Cache Controller

DU Hui-min; YANG Chao-qun; JI Kai-bo

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Design and Implementation of Embedded GPU Cache Controller

更新时间：2026-09-04

- Design and Implementation of Embedded GPU Cache Controller
- Vol. 35, Issue 2, Pages: 94-99(2018)
- 作者机构：
  
  西安邮电大学机构电子工程学院,陕西,西安,710121
- 作者简介：
- 基金信息：
- DOI：
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- Published：2018
- 稿件说明：
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杜慧敏, 杨超群, 季凯柏. 嵌入式GPU中二级高速缓存的设计与实现[J]. 微电子学与计算机, 2018, 35(2): 94-99.

DU Hui-min, YANG Chao-qun, JI Kai-bo. Design and Implementation of Embedded GPU Cache Controller[J]. 2018, 35(2): 94-99.
杜慧敏, 杨超群, 季凯柏. 嵌入式GPU中二级高速缓存的设计与实现[J]. 微电子学与计算机, 2018, 35(2): 94-99. DOI：

DU Hui-min, YANG Chao-qun, JI Kai-bo. Design and Implementation of Embedded GPU Cache Controller[J]. 2018, 35(2): 94-99. DOI：

摘要

针对嵌入式GPU与主存之间进行数据交互时出现速度不匹配的问题

设计了一种适用于嵌入式GPU的二级高速缓存Cache控制器.二级Cache控制器采用四路组相联的映射结构

使用伪最近最少使用(Pseudo_LRU)替换算法

可以管理16~512 kB的二级高速缓存.实验结果表明

当选取Cache大小为128 kB时

Cache的命中率达到71.12%.

Abstract

A suitable for embedded GPU cache controller is designed for the speed mismatch problems data interaction between main memory and embedded GPU. The cache controller adopts a four-way set associative mapping structure

uses pseudo-Least Recently Used replacement algorithm. The size of CacheSRAM can be configured

which configuration range is 32~512 kB. The experimental results show that when the CacheSRAM capacity is 128 kB

hit rate of the graphics applications Cache can reach to 71.12%

the cache controller can further enhance the overall performance of embedded GPU.

关键词

Keywords

references

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