A High Performance Hardware Design for HEVC Integral Motion Estimation

LIU Kai-li; CHEN Cheng; LI Yao; CHEN Song

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A High Performance Hardware Design for HEVC Integral Motion Estimation

更新时间：2026-09-04

- A High Performance Hardware Design for HEVC Integral Motion Estimation
- Vol. 34, Issue 10, Pages: 81-85(2017)
- 作者机构：
  
  中国科学技术大学电子科学与技术系,安徽,合肥,230027
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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刘凯丽, 陈成, 李垚, 陈松. 一种高性能HEVC整像素运动估计硬件设计[J]. 微电子学与计算机, 2017, 34(10): 81-85.

LIU Kai-li, CHEN Cheng, LI Yao, et al. A High Performance Hardware Design for HEVC Integral Motion Estimation[J]. 2017, 34(10): 81-85.
刘凯丽, 陈成, 李垚, 陈松. 一种高性能HEVC整像素运动估计硬件设计[J]. 微电子学与计算机, 2017, 34(10): 81-85. DOI：

LIU Kai-li, CHEN Cheng, LI Yao, et al. A High Performance Hardware Design for HEVC Integral Motion Estimation[J]. 2017, 34(10): 81-85. DOI：

摘要

针对整像素运动估计提出了一种适合硬件实现的运动估计算法

并设计了硬件架构.通过在不同划分深度的编码单元中复用计算单元

大大减少了硬件资源.在TSMC 90nm的工艺下

综合结果表明最高频率可以达到377 MHz

在搜索范围为±64时

能够达到超高清视频图像3 840×2 160@60 f/s的实时处理速度.

Abstract

In this paper

a motion estimation algorithm suitable for hardware implementation is proposed for integer motion estimation

and the hardware architecture is also presented. By reusing computing unit in the CU depths

the hardware resource is greatly reduced. Synthesized results in the TSMC 90nm show that the frequency of presented architecture can reach 377 MHz and the throughput can achieve 3 840×2 160@60 f/s real-time processing in the search range of ±64

which meets the requirement of processing HD video images in real time.

关键词

Keywords

references

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Zhou D, Zhou J, He G, et al. A 1.59 Gpixel/s motion estimation processor with 211 to+ 211 search range for UHDTV video encoder[J]. IEEE Journal of Solid-State Circuits, 2014, 49(4): 827-837. DOI: 827

Sinangil M E, Sze V, Zhou M, et al. Cost and coding efficient motion estimation design considerations for high efficiency video coding (HEVC) standard[J]. IEEE Journal of selected topics in signal processing, 2013, 7(6): 1017-1028. DOI: 1017

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Chen C Y, Chien S Y, Huang Y W, et al. Analysis and architecture design of variable block-size motion estimation for H. 264/AVC[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2006, 53(3): 578-593. DOI: 578

陈伟伟, 朱惠, 何卫锋, 等. 一种面向HEVC运动估计的高性能VLSI架构[J]. 微电子学与计算机, 2013, 31(6): 10-14. DOI: 10

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