A 10-bit 300 MSPS DAC With Variable Gain Based on 28nm Process

XIONG Li-wei; DU Zhan-kun; LIU Ke; MA Xiao; PANG Xiao-min

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A 10-bit 300 MSPS DAC With Variable Gain Based on 28nm Process

更新时间：2026-09-04

- A 10-bit 300 MSPS DAC With Variable Gain Based on 28nm Process
- Vol. 34, Issue 11, Pages: 89-93(2017)
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 中国科学院大学机构,北京,101408
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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熊利伟, 杜占坤, 刘珂, 马骁, 庞晓敏. 一款增益可调的28 nm三通道10位DAC[J]. 微电子学与计算机, 2017, 34(11): 89-93.

XIONG Li-wei, DU Zhan-kun, LIU Ke, et al. A 10-bit 300 MSPS DAC With Variable Gain Based on 28nm Process[J]. 2017, 34(11): 89-93.
熊利伟, 杜占坤, 刘珂, 马骁, 庞晓敏. 一款增益可调的28 nm三通道10位DAC[J]. 微电子学与计算机, 2017, 34(11): 89-93. DOI：

XIONG Li-wei, DU Zhan-kun, LIU Ke, et al. A 10-bit 300 MSPS DAC With Variable Gain Based on 28nm Process[J]. 2017, 34(11): 89-93. DOI：

摘要

基于SMIC 28 nm CMOS工艺

实现了一款增益可调的三通道的300 MS/s 10 bit的数模转换器.此数模转化器可以通过5位的控制字实现0~-5.75 dB的增益调节

适应更多的应用环境.数模转换器采用分段式结构

其中高六位采用温度计码

低四位采用二进制码.在电流源单元开关部分采用限幅电路

提高无杂散动态范围.带隙基准单元采用低电压输出结构

满足电压电流转换单元中的栅压要求.在1.8 V模拟电源电压

1.05 V数字电压下

采样时钟在300 MHz的时候

无杂散动态范围(SFDR)为64 dB

微分非线性小于(DNL)±0.3 LSB; 积分非线性小于(INL)±0.4 LSB.

Abstract

This paper presents a variable gain three-channel 10-bit current steering CMOS digital-to-analog converter (DAC) implemented in a standard 28-nm CMOS technology. The DAC achieved variable gain of 0~-5.75 dB with five-bits control words to apply to a wider range of applications. The DAC is segmented as 6+4

where the 4-LSB bits are implemented in binary and the 6-MSB bits are implemented in unary architecture. The spurious free dynamic range (SFDR) of this DAC can be improved by using clipper circuit in the part of switches. The reference voltage of bandgap must be low enough to meet the requirements of bias voltage in the part of voltage changing to current. The circuit is fabricated in 1.8-V analog power supply and 1.05-V digital power supply. For sampling frequencies up to 300MSample/s

the SFDR is better than 64 dB. The measured differential nonlinearity and integral nonlinearity are 0.3 least significant bit (LSB) and 0.4 LSB

respectively.

关键词

Keywords

references

孔瀛, 王宗民, 许军. 一种16位高速数模转换器(DAC)的设计与实现[J]. 微电子学与计算机, 2011, 28(6): 31-35. DOI: 31

Pieter Palmers, Michiel S.J. Steyaert. A 10-Bit 1.6-GS/s 27-mW current-steering D/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS[J]. IEEE Trans. Circuits Systems, 2010, 57(11): 2870-2879. DOI: 2870

Marcel J M Pelgrom. Matching properties of MOS transistors [J]. IEEE Journal of Solid-State Circuits, 1989, 24(5): 1433-1439. DOI: 1433

A Van den Bosch, M Steyaert, W Sansen. SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters[J]. IEEE International Conference on Electronics, Circuits and Systems, 1999, 3: 1193-1196. DOI: 1193

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