Implementation of Open Loop Phase Modulator

JIANG Xue-ping

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Implementation of Open Loop Phase Modulator

更新时间：2026-09-04

- Implementation of Open Loop Phase Modulator
- Vol. 34, Issue 7, Pages: 88-91(2017)
- 作者机构：
  
  全球能源互联网研究院,北京,102211
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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姜学平. 开环相位调制器实现技术[J]. 微电子学与计算机, 2017, 34(7): 88-91.

JIANG Xue-ping. Implementation of Open Loop Phase Modulator[J]. 2017, 34(7): 88-91.
姜学平. 开环相位调制器实现技术[J]. 微电子学与计算机, 2017, 34(7): 88-91. DOI：

JIANG Xue-ping. Implementation of Open Loop Phase Modulator[J]. 2017, 34(7): 88-91. DOI：

摘要

为了提高极坐标发射机可以支持的数据率

研究了宽带开环相位调制器的实现技术

并基于65nm CMOS工艺实现了该款开环相位调制器电路

其版图面积仅为0.2m

功耗为13mW

平均相位步长为0.703°

DNL为0.525LSB.

Abstract

In order to improve the polar transmitter can support the implementation of data rate

this paper studies the technology of broadband open loop phase modulator

and based on 65 nm CMOS technology to achieve the openloop phase modulator circuit

the chip area is only 0.2 um

power is 13 mW

the average phase step DNL for 0.525 LSB.

关键词

Keywords

references

Kreienkamp R, Langmann U, Zimmermann C, et al. A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator[J]. Solid-State Circuits, IEEE Journal of, 2005, 40 (3): 736-743. DOI: 736

Song Z, Liu X, Jin Z, et al. A 180nm CMOS wireless transceiver by utilizing guard band for narrowband IoT applications[C]//Solid-State Circuits Conference (ASSCC), 2015IEEE Asian. IEEE, 2015: 1-4.

Ye L, Chen J, Kong L, et al. Design considerations for a direct digitally modulated WLAN transmitter with integrated phase path and dynamic impedance modulation[J]. Solid-State Circuits, IEEE Journal of, 2013, 48 (12): 3160-3177. DOI: 3160

Staszewski R B, Wallberg J L, Rezeq S, et al. Alldigital PLL and transmitter for mobile phones[J]. Solid-State Circuits, IEEE Journal of, 2005, 40 (12): 2469-2482. DOI: 2469

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