Design and Implementation of a 65 nm CMOS Clock Generator

GAO Hui; LIU Wen-ping

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Design and Implementation of a 65 nm CMOS Clock Generator

更新时间：2026-09-04

- Design and Implementation of a 65 nm CMOS Clock Generator
- Vol. 34, Issue 9, Pages: 107-111(2017)
- 作者机构：
  
  西安微电子技术研究所,陕西,西安,710054
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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高辉, 刘文平. 65 nm CMOS工艺时钟发生器的设计与实现[J]. 微电子学与计算机, 2017, 34(9): 107-111.

GAO Hui, LIU Wen-ping. Design and Implementation of a 65 nm CMOS Clock Generator[J]. 2017, 34(9): 107-111.
高辉, 刘文平. 65 nm CMOS工艺时钟发生器的设计与实现[J]. 微电子学与计算机, 2017, 34(9): 107-111. DOI：

GAO Hui, LIU Wen-ping. Design and Implementation of a 65 nm CMOS Clock Generator[J]. 2017, 34(9): 107-111. DOI：

摘要

设计了一款应用于高速片上系统(System-on-Chip

SoC)领域的时钟发生器电路.基于Delta-sigma调制技术实现了小数分频

同时引入了加抖技术(Dither)以及模数转换器(Digital to Analog Converter

DAC)补偿技术

从而大幅度地抑制了Delta-sigma调制引起的量化噪声.基于65 nm CMOS工艺完成了电路设计

仿真结果表明

当输出频率为典型应用的1.2 GHz时

该电路周期抖动(period jitter)的均方根值(rms)约为0.656 ps

功耗仅为约3.824 mW.

Abstract

This paper introduces a clock generator intended for the use in a high-speed SoC design. Fractional division achieved through the employment of Delta-sigma modulation. Significantly suppression of quantization error

which is caused by the Delta-sigma modulation

obtained through the use of dithering and DAC compensation technology. Circuit design implemented based on a 65 nm CMOS process and the simulation result shows that the period jitter (rms) and the total power are 0.656 ps and 3.824 mW

respectively

when the output frequency is 1.2 GHz of a typical application.

关键词

Keywords

references

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胡帅帅, 周玉梅, 张锋. 10GHz扩频时钟发生器的设计[J]. 微电子学与计算机, 2016, 33(10): 63-67. DOI: 63

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