A New Tracking SAR ADC

YU Bao-liang; FENG Hai-gang

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A New Tracking SAR ADC

更新时间：2026-09-04

- A New Tracking SAR ADC
- Vol. 35, Issue 1, Pages: 124-127(2018)
- 作者机构：
  
  清华大学深圳研究生院,广东,深圳,518055
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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于宝亮, 冯海刚. 一种新型跟踪式逐次逼近模数转换器[J]. 微电子学与计算机, 2018, 35(1): 124-127, 132.

YU Bao-liang, FENG Hai-gang. A New Tracking SAR ADC[J]. 2018, 35(1): 124-127.
于宝亮, 冯海刚. 一种新型跟踪式逐次逼近模数转换器[J]. 微电子学与计算机, 2018, 35(1): 124-127, 132. DOI：

YU Bao-liang, FENG Hai-gang. A New Tracking SAR ADC[J]. 2018, 35(1): 124-127. DOI：

摘要

为了降低功耗和复杂度

采用复用量化器结构

而不需要传统结构中的减法和数模转换器模块(DAC)

实现一低功耗简单的跟踪式模数转换器.量化器采用8bit电容单调式切换的逐次逼近模数转换器(SAR ADC).另外为了进一步提高效率

SAR ADC中的比较器采用时间域比较器实现.经过在90 nm CMOS工艺下仿真验证

设计的ADC采样速度16 MHz

8倍过采样率(OSR).经过数字滤波处理

输入信号频率为227 kHz时

可以实现59.6 dB的信噪失真比(SNDR)

功耗28.5 W

品质因数(FOM) 18.4 fJ/step.另外

由于转换过程主要在数字域实现

这种ADC便于移植到更先进的工艺

并获得更好的效率.

Abstract

This paper presents a tracking analog-to-digital converter (ADC).By reusing the quantizer

the tracking ADC no long needs subtraction and digital-to-analog (DAC) module that the conventional structure needs.This technique could decrease the power consumption and the chip area.The quantizer adopts 8-bit monotonic switching scheme successive-approximation-register (SAR) ADC.In addition

to further increase efficiency

a time domain comparator is used to replace the analog domain comparator.This ADC is simulated in a 90 nm CMOS technique.It works with 16 MHz sampling rate

8 over sampling rate (OSR).It achieves 59.6 dB SNDR for an input signal around 227 KHz with the help of a simple digital low pass filter.Counting in the filter

it consumes 28.5 W power under 1-Vsupply.The figure-of-merit (FOM) is 18.4 fJ/STEP.In addition

such topology bring us the advantage of easy design migration among technology nodes for seeking greater efficiency improvement.

关键词

Keywords

references

Jeffrey Fredenburg, Michael Flynn. A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-Shaping SAR ADC[C]//International Solid-State Circuits Conference Papers. IEEE, 2012: 468-469.

Andrea Agnes, Edoardo Bonizzoni, Piero Malcovati, et al. A 9.4-ENOB 1V3.8uW 100KS/s SAR ADC with Time-Domain Comparator[C]//International Solid-State Circuits Conference Papers. IEEE, 2008: 246, 610.

Liu Chun-Cheng, ChangSoon-Jyh, HuangGuan-Ying, et al. A 0.92mW 10-bit 50MS/s SAR ADC in 0.13μm CMOS Process[C]//Symposium on VLSI Circuits Digest of Technical Papers. IEEE, 2009: 236-237.

ChenYan-Jiun, HsiehChih-Cheng. A 0.4V2.02fJ/Conversion-step 10-bit Hybrid SAR ADC with Timedomain Quantizer in 90nm CMOS[C]//Symposium on VLSI Circuits Digest of Technical Papers. IEEE, 2014: 1-2.

汪荔, 贺林. 一种11位过采样跟踪型SAR A/D转换器[J]. 微电子学, 2016, 37(1): 5-8. DOI: 5

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